CA1087320A - Semiconductor switching device - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE

The disclosed PNPN device includes a first base layer thicker than the remaining layers and formed of a low and a high resistivity semiconductor layer superposing each other. The low resistivity layer is partly exposed to one of the main races of the device with a first emitter layer and provided with a control electrode adapted to-be applied with a reverse voltage.

Description

` ` ~OIB7320 This invention relates to improvements in a semiconductor switching device and more particularly to improve-ment in the turn-off characteristic of PNPN four layer semi-conductor switching devices.
Among conventional PNPN four layer semiconductor switching devices there are well known gate turn-off thyristors and gate assisted turn-off thyristors utilizing both the reverse biasing of the gate electrode and that of the anode electrode.~
1~ ~n such switching devices it has been difficult to decrease a lateral or sheet resistance of the base region to which the control or gate electrode is attached, and therefore to improve the turn-off capability of the devices.
Accordingly, it is an object of the present invention to provide a new semiconductor switching device improved in turn-off capability.
SUMMARY OF THE INVENTION
According to the present invention there is provided a semiconductor gate turn-off switching device comprising a semiconductor substrate including a pair of opposed main faces, a first semiconductor layer having a first conductivity type and having a first surface exposed to a first one of said main faces of said semiconductor substrate, a second semiconductor layer having a second conductivity type, having a second surface exposed to said first main face of said semiconductor substrate and forming a first PN junction with said first semiconductor layer, a means for applying a reverse voltage across said first PN junction, a third semiconductor layer having a first conductivity type forming a second PN junction with said second semiconductor layer, and a fourth semiconductor layer having a second conductivity type, having a third surface exposed to a second one of said main faces of said semiconductor substrate

-2- ~
~ .

-` 1087320 and forming a third PN junction with said third semiconductor layer, a first main electrode disposed in ohmic contact with said first surface of said first semiconductor layer, and a second main electrode disposed in ohmic contact with said third surface of said fourth semiconductor layer, and a control electrode disposed in ohmic contact with said second surface of said second semiconductor layer, wherein said second semi-conductor layer is thicker than said third semiconductor layer.
Preferably, the second semiconductor layer may be -formed of a low resistivity semiconductor layer and a high resisitivity semiconductor layer, the low resistivity semiconductor ~ :
layer including a surface exposed to the one main face of the ` ~:
semiconductor substrate and connected to the control electrode and the low resistivity semiconductor layer is interposed -.
between the first semiconductor layer and the high resistivity :
semiconductor layer to form a low resistance layer. - .
. In order to increase a reverse breakdown voltage of the first PN junction, a semiconductor layer higher in resistivity than the exposed portion of the first semiconductor layer may be disposed adjacent the first PN junction at the interface between ~ ~ -3-.. , : .

` -- " 10~7320 . .`
the first semiconductor layer and the second semiconductor layer.
BRIEF DESCRIPTION OF THE DRAWINGS
The present invention will become more readily apparent from the following description taken in conjunction with the accompanying drawings in which: :
Figure 1 is a schematic cross sectional view of a PNPN
four layer semiconductor switching device constructed in accordance with the principles of the prior art;
Figure 2A is a schematic cross sectional view of a PNPN
four layer semiconductor switching device constructed in accord- ~ ;
ance with the principles of the present.invention;
Figure 2B is a view similar to Figure 2A ~ut illustrat- ~-ing a modification of the arrangement shown in Figure 2A; -Figure 3A is a schematic cross sectional view of a modi- . :
fication of the present invention;
Figure 3B is a view similar to Figure 3A but illustrat-ing a modification of the arrangement shown in Figure 3A;
Figure 4A is a schematic cross sectional view of another modification of the present invention; :. .
Figure 4B is a schematic plan view of the arrangement shown in Figure 4A with some parts omitted; ~ :
Figure 5A is a schematic cross sectional view 10873~:0 is still another modification of the present invention;
~ i~ure 5B is a view similar to Figure 5A but illustrating a modi~ication of the arraLgement shown in Figure 5A; a~d ~ igule 6 i9 a ~raph illustrating the current-to-voltag~ curve depicted in th~ ON and OFF states of the semiconductor switchirg device of the present i~ven~i~n and also upon switching its O~ to its CFF
state thereof, Throughout the ~igures except fcr ~igure 6 like reference numerals designate the identical Gr corresponding components.

- EESCRIPTTON OF TKE PRE~ RED EMBODILENTS

Referring now to Figure 1 of the drawings, there is illustrated a notion~l structure of one type of ~ell known PNPN four layer semiconductor switching devices such as gate turn-off thrristors and gate assisted turn-off thyristors utilizing both the reverse bia~ing of the gate electrode and that of the anode electrode. The arrangement illustrated comprises a semico~ductor substrate 10 including a first transistor composed of a first P type semiconductor layer 12, a second N type semiconductor layer 14 and a third P type semiconductor layer 16 and a second transistor composed of the second N type semiconductor layer 14, the third P type semiconductor layer 16, a~d a fourth N type semiconductor l~yer 18 consiYting ~ 1087320 oP an annu~ar N type semiconductor layer portion and a central N type semiconductor layer portion disposed on the third semiconductor layer 16.
In the first transistor the P type semiconductor layer 12 serving as an emitter region is expo~ed to one of the opposite main faces in this case, the uppsr main face of the substrate 10 and forms a first PN
~unctions J1 witb the second N type semiconductor layer U , and the second Qemiconductor layer 14 has the ability to block voltages because of its high resistivity, Then the secDnd N type semiconductDr layer 14 form~Q as second PN junction J2 with the third P type semiconductor layer 16 thinner than the lager 14.
The second transistor includes the ~econd PN
~unction J2 and three discrete third PN junctions J3 formed betveen the third P type semiconductor layer 16 and the central and annular N type semiconductor layer porti~ns forming tbe fourth layer lg exposed to .
the other or lower main face of the substrate 10.
Also the third layer 16 i9 partly exposed to the lower main faoe of the substrate 10. In the second transistor the P type semiconductor layer 16 serYes as a base region while the N type layer 14 provides as emitter region.
In all the Figures except for Figure 6, the conductivity of the emitter or ba_e region i_ designated by the reference character identifying the cDnductivity of the semiconductor materi~l forming , .~ ",.. . . .

~ ` 10~7320 that region and suffixed with the reference character "e" or '~" For example, Pb designates the conductivity of the third semiconductor layer 16 serviog as the base region.
A first main electrode, in this case, an anode electrode 20 i~ disposed in ohmic contact with the exposed surface of the first semiconductor layer 12 and conn~cted to a first main terminal Y while a second main electrode or a cathode electrode 22 i9 ~ormed of a central and an annular electrode portioLo dispo~ed in ohmic cDntact with the central and annular semiconductor l~yer portions forming the fourth layer 18 and connected together to a second main terminal Y. Then a gate electrode 2~ includes an annular gate electrodè portion disposed in ohmic contact with the peripheral portion of the exposed surface of the third æemiconductor l~yer 16 and another annular gate portion disposed in ohmic contact with that portion of the exposed surface of the third layer 16 located between the fourth annular and central layer portions 18. The gate electrode portions 24 are concentric ~ith each other and connected together to a gate terminal G.
A gate source of direct current 26 ~is connected acroæs the second main terminal Y and the gate terminal G through a ~witch 2g to bias the gate electrode 2~ 90 as to negative with reæpect to the cathode electrode 22. Another W gate source 26 i9 ~milarly connected acros~ those terminals - . : . ., . . .

~01~7320 to bla~ the gate electrode 24 90 as to be positive ~ith respect to the cathode electrode 22.
The first transi~tor ha~ a rate of carrier in~ection or a current amplific~tion factor less than that of the second transistor.
Conventio~al PNPN four layer devices such as shown i~ Figure 1 ha~e had tbe following disadvantage~:
Upon turn-off, a reverse voltage from the source 26 i9 applied to th0 gate electrode 24 to draw carriers out from the third semiconductor layer 16 interpo~ed between the second and fourth semiconductor layers U
and 18 re~pectively through the gate èlectrode 2~.
This third layer i8 called hereinafter a "control gate lsyer~. As the turn-off proces~ proceeds~
current paths due to the carriers in~ected from the first semiconductor l~yer 12 are concentrated ;~
in a position furthest remove aw~y from the gate electrode 24, tbat i9 to say, the central portion of tbe fourth aemiconductor l~yer 18 as shown at the arro~
I in Figure 1.
On the other hand, the third lager 16 or the control g~te layer througb which tbe current paths estend has a sbeet resistance ~ (see Figure 1) to ~hich the gate electrode is attached and is small in tbickness because tbe current amplification degree ia imparted mainly by the second transistor 14-16-18 as above described. Therefore the sheet resistance become high a~d a voltage drop across the high re~istano~ ~ has made it difficult to rev~rsely bias , : ,. . . .
- .:
. . . . .

that third junction J3 located on the central portion of the fourth semiconductor l~yer lg furthest remote away from the gate electrode 24. If the third semiccnductor layer 16 is formed of a low resistivity semiconductive material to decrea~e the resistance ~
tben a reverse voltage withstood by the th~rd junction J3 is decreased untll that portion of the third ~unction J3 near to the gate electrode 24 ~ill be first broken down in the reverse direction.
In the arrangement of Figure 1 only a mea~ure decreasing the resistance ~ has been to provide a small lateral dimension of the central pDrtion of the fourth semiconductor l,ayer 1~, which, in turn, decreases an area occupied by tbe fourth semiconductor la~er 18. This area forms the effectlve area for a current flowing through the fourth semiconductor layer 18. Also it has been required to provide a complicated fine pattern in which the third and fourth semic~nductor layers are exposed to the other main face of the substrate 10. This ha~ been attended with a high rate of the oc¢urrence of defe¢ts in the sub~trate and therefore such a pattern has been difficult to be formed in view of the manufacturing steps. With tbe pattern easilr formed, ~t has been difficult to decrease the resistance r~ to a sufficiently low magnitude. E~entuall~ there has been no measures but to extremely decrease the mean density of a curre~t flowing thrcugh an asseciated semicDnductor substrate.

The present invention contemplates to eliminate the disadvantages of the prior art practice as abovde described.
Referring now to Figure 2A, there i9 illustrated PNPN four layer semiconductor s~itching device constructed in accordance with the principles o~ the present invention.
The arra~gement illustrated comprise a se~iconductor substrate 10 including a pair of first and second main faces, a first P type semiconductor layer 12 consisting of an annular and a central portion expo~ed to the peripherP~ edge and central portions of the first main face, in this case, the upper main face of the substrate .^
10 and a second N type semiconductor layer 14a expo~ed to the remalning portion Df the first main substrate face and overlain by the first P type l~yer 12 to form three aiscrete first PN ~unctlon Jl therebetween.
The N tgpe semiconductor layer 14a iæ continuous to an ~ type semiconductor layer 14b to form an N type semioonductor lager U corresponding to the N type semicondu¢tor layer U as shown in Figure 1. The i type semiconductor layer 14_ is disposed on a third P type semiconductor layer 16 to form a second PN
~unction J2 between the N and P type semiconduct~r layer~ 14 and 16 respectively.
The other main face of the sub~trate 10 is formed of a fourth N type semiconductor layer lg disposed on the third P t~pe semiconductor layer 16 to form a third PN junction J3 therebetween.
As in the arrangement of ~lgure 1, the first, .

10~373Z0 second and third ~emiconductor layers form a first transistor while the second, third and fourth semiconductor layers form a second transistor.
An annular and a central electrode 20 are disposed in ohmic contact witb the annular and central portions of the first N type semiconductor layer 12 and connected together to a first main terminal ~. Those electrodes form a first main electrode 20, in this case, an anode electrode A ~econd main electrode 22 or a cathode electrode is disposed in ohmic contact with the fourth semiconductor layer 18 and connected to a second main terminal Y.
An anDular contrDl electrode 2~ called the gate electrode in the arrangement of ~igure 1 is disposed in ohmi¢ contact with the exposed portion of the N
type semiconductor layer 14a to be located bet~een the central and aDnular aDode electrodes 20. Un-ike the arrangement of Figure 1~ the third semiconductor la~er 16 is not expo~ed to the other main face of the substrate 10.
A control source of direct current 26 is sho~n in Flgure 2A a9 includi~g a negative side connected to the first main terminal Y and a positive side connested to a co~trol terminal C to whi¢h the control electrDde 24 i9 connected.
The arrangement of Figure 2A is turned on by having a voltage applied across the anode and co~trol electrodes 20 and 2~ respectively with a polarity reversed from that of control voltage . .; .; ~.; ~, :. :

shown by -VcA in Figure 2A.
From the foregoing it i9 seen that in the present invention the second semiconductor layer 14 thicker than the remaining la~ers is exposed to the rirst main face of the substrate 10 and the control electrode 24 i9 disposed in ohmic contact with the exposed surface of the secDnd semiconductor layer 14, In the forward blocki~g state~ a reverse ~olt~ge is applied across the second ~unction J2 to spread ...
a depletion layer adjacent to that junction to~ard the ~e¢ond semiconductor la~er 14. Thus the second semiconductor lager 14 has an increased thickness sufficient to spread the depletion l~yer as required, ;
In the arra~gemeLt of Figure 2A, the control is accomplished by the first transistor 12-14-16 having a low current amplification factor resulting in an increase in control current -Ic from the control source 26 for reversely bi~sing the second junction J2.
Ho~ever, since the second semiconductor lager 14 has a thicknesn ver~ large as compared with tbe remaining semlconductor lager~, a current ha~ing flowed through the anode electrode 20 and the fir t semiconductor layer 12 is actually commutated directly to the second semiconductor layer 12 tbrough the control electrode 2~.
This mean~ that tbe ~econd semiconductor layer 14 is low in sheet resistance Ec (see Figure 2A).
In order to further decrease this sheet resistance, that side of the second semicDnductDr la~er 14 near to thé second junction J2 has been formed ~os7320 of a lightly doped semiconductor layer 14b having a high resistivity and therefore a lo~ impurity concentration. The layer 14b may be of an i or a )v type semiconductive material.
In addition, that portion of the second semiconductor layer 14 ne~r to the first ~unction Jl has been formed of a semiconductive material highly doped with ~n impurity in the example illustrated, a P type impurity to have a low resistivity.
Therefore this lo~ resistivity layer is of pt type and a thickness x2 (see ~igure 2A) thereof can be greater than a thickness ~ of the third semiconductor layer 16 forming the base region of the second transistor.
m i~ is because the second semiconductor layer 14 forms a base region of that transistor having a low current ampli~ication factor. Therefore the layer 14 can easily increase in thickness.
~or example, tb0 third semiconductor layer has a thickness X3 ranging fr~m several microns to scores of microns while the thickness x2 of the second semiconductor layer 14 may range from scores to hundreds of microns. Also the low resistivity layer 14a may ha~e *ts thickness ~ equsl to from one slxth to t~o thirdsthe thickness x .
In this way the sheet resistance r of the second semioonductor layer 14 and more particularly of the low resistivity layer 14a has been extremely low. As a result~ a control voltage -VcA required for the principal current I to be commutated, as a current -Ic through the control electrode 24, . .
. , ., .;: : :

1087;~20 is decreased in the absolute magnitude. In this case, the absolute magnitude of the control current -Ic is not greater higher than that of the principal current I nnd may be greater than the latter at the beginning of the turn-off process. Alternatively, with the conditions for the control voltage remaining unchanged, tbe central portion of the first semiconductor layer 12 exposed to the ~irst main face of the suhstrate 10 may rather have a diameter ;~
(see Figure 2A) increased. This results in a decrease in finene~s of the particular p~ttern to facilitate the manufacture thereof.
Figure ~B sho~s a modification of the arrangement illustrated in Figure 2A. The arrangement illuotrated is different frDm that shown in Figure 2 only in that in ~igure 2B the components bave the conductivity reversed fr~m that illustratea in Figure 2 with the sources poled accordingly. For example, Figure 2A sbows the second semiconductor layer with an N type conductivity operatively connected to the control electrode while Figure 2B shows that having a P~ type conductivity. In Figure 2B, the layer l~b may be of an _ or s~ type semiconductive material Figure 3A shows a modification of the present invention. The srrangement illustrated is different from that shown in Figure 3A only in that in Figure 3A, a thin semiconductor layer is disposed ad~acent to the interface between the first and second :

semiconductor layers 12 and 14a or the junction Jl within the second semiconductor layer 14a exposed to the first main face of the substrate 10. This thin semiconductor layer 30 is higher in resistivity than the exposed portion of the first semiconductor layer 12 and may be of either an N or a P type. An N or a P
type layer is higher in resistivity, or less in impurity concen-tration than an N or a P type layer. If the semiconductor layer 30 is of the N type then the discrete first junctions Jl are ;~ -formed in solid line Jl' On the other hand, the use of the P
type layer 30 results in the formation of the first junctions in dotted line adjacent to the solid line Jl' In Figure 3B, the components have the conductivity reversed from that illustrated in Figure 3A with the sources (not shown) poled accordingly. In other respects, the arrangement is -identical to that shown in Figure 3A.
In Figure 3B, therefore, the thin semiconductor layer ~;
30 with a P type conductivity forms the discrete first junctions in solid line Jl with the first semiconductor layer 12 while the layer 30 having an N type conductivity and semiconductor layer 12 form the first junctions in dotted line adjacent to the solid --~
line J. ~ -In the arrangements as shown in Figures 3A and 3B, a ;
reverse breakdown voltage for the first PN junction Jl is increased thereby to permit a higher control voltage -VcA to be applied thereacross.

.

.

1~137320 This cooperates with a decrease in sheet reslstance rc as above .;
described to permit a higher currents to be turned off.
In another modification of the present invention shown in Figures 4A and 4B, the semiconductor substrate 10 includes a : :
bevelled peripheral wall and the first semiconductor layer 12 in .
the form of a plurality of radial strips disposed at substantially equal angular intervals. As best shown in Figure 4B wherein the ~:
anode and gate electrodes 20 and 24 respectively omitted only for purposes of illustration, the radial strips forming ~he first semiconductor layer 12 radially extend between a pair o~ concen-tric circles as shown at dotted line i~.Figure 4B also concentric with the circular substrate 10 and each strip includes circumfer-entially extended short branches.
Further the substrate 10 is fi~edly secured to a cir-cular base plate 32 of any suitable electrically conductive mat-erial such as copper, molybdenum, tungsten or the like as by brazing the cathode electrode 22 to the base plate 32. -Therefore, in the present invention, a pattern in which the first and second semiconductor layers 12 and 14 respectively are disposed on one of the main faces of the substrate 10 can be made similar to the pattern in which the base and emitter regions are disposed in conventional transistors and also to the patterns of the gate and cathode regions used .-: . ,,, ; ~

~B732~

in conventional gate turn-of~ and gate assisted turn-off thyris- ;~
tors. With the finess of the pattern remaining unchanged, a current capable of being turned off becomes high. Alternatively, with a current to be turned off remaining unchanged, the finess ~ ~-of the particular pattern is decreased to facilitate the manu-facture.
Figure 5A shows still another modification of the present invention applied to a reverse conducting device and Figure 5B shows a modifica~ion thereof similar to that illustrated in Figure 5A except for the conductivity of the components. That :;.
is, the arrangement of Figure 5A includes an N type control gate layer 14 and that of Figure 5B includes a P type control gate layer 14.
As shown in Figure 5A, the first P type semiconductor layer 12 is iIi the form of two concentric annuli disposed on the ~ .
one main face of the substrate 10 and a pair of first main elec~
trodes 20, in this case, anode electrodes are disposed in ohmic .
contact with the two annuli of the first P+ type semiconductor ~:
layer 12. It is to be noted that the outer annulus of the electrode 20 is also disposed in ohmic contact with the exposed ~-surface portion of the second N type semiconductor layer 14.
Further the other main face of the substrate 10 includes the central portion to which the fourth N type semiconductor layer 18 is entirely exposed and the peripheral portion to which the peripheral portion -1~87320 of the third P type semico~ductor l~yer 16 is expo~ed.
Then a ~ingle second main electrode 22~ in this case, a cathode electrode is disposed in ohmic contact ~ith the other main substrate face throughout the entire area and then ~uitably fixed to a ba~e plate 32 o~
an electricallg conductive material such a~ above de~cr~be.
In Figure 5~, the fourth semiconductor layer 18 is shown a~ having a radiu~ less ~ than the outside radius of the outer a~nulus of the n rst semiconductor la~er 12~ Also it is seen that those portions of both electrodes 20 and 22 coLtacted by the second and tblrd semiconductDr l~yets 1~ and 16 respecti~ely form a semiconductor diode with those portions of the l~yers 12 and 1~ located therebet~een.
The dlode includes tbe perlpheral portion of the second ~unction J2.
Therefore the arrangement of Figure 5A
comprises a PNPN s~itching devioe surrounded by a semiconductor diode. Since suoh a device is not applied witb a reverse voltage, the high resist$~ity sem~oondlctor l~yer 14~ ma~ decrease in thloknese.
Thus the low resisti~it~ l~yer l~b can easily increa6e in thlcknes~. Thi4 results in the facilitation of a rurther decrease in ~heet resistance rc f the layer 14a.
In PNPN s~i~cbi~g deviceo bavi~g tbe re~erse blockiDg voltage less tban tbe for~ard blocking voltage, tbe peripheral surface o~ the ~emiconductoi substrate ~0~373ZO

may be subjected to the positive bevelling thereby to increa~e a rate at which the area Df the semiconductor ~afer can be utilized. In the positive bevelling a tilted angle to either one or the other of main fsce~
of the substrate approaches 50 degrees and normally is on the order of 60 degrees as shonn in Figures 4 and 5.
In the arrangements as sho~n in Figures 2 to 5, the control electrode 24 is disposed on the one main face of the semiconductor substrate 10 to which the first semiconductor layer 12 is exposed so that the second main electrode 22 on the side of the fourth semiconductor l~yer 18 becomes flat. Then the base plate 32 as above described can be fixedly secured to that flat surface of the second main electrode. ID this case, the positi~e bevelling permits the cross sectionPl pro~ile of the substrate to have an acute angle located OD the base plate. In other words, the substrate includes the other main face broader m area than the one main face. This cooperates ~ith a positively bevelled angle approacbing 90 degrees to make it difficult to break or damage the semiconductor substrate.
On the contrary, conventional devices such as shown in Figure 1~ have included the one main face to whicb a base plate is attached and also tbe first semiconductor layer is exposed. Under these circumstances, the positive bevelling causes a decrease in area of the one main substrate ~ace.
Therefore the semiconductor substrate or wafer has . .. ....... .. , -- .

~ 1087320 a cross secti~nal profile including an acute angle located on that side thereof remote from the base plate.
This results in the easy break or damage of the semiconductor wafer. This is avoided thr~ugh the negative bevelling but the resulting cross sectional profile will include an angle of several degrees.
Thus th0 semiconductor wafer has a decreased rate of utilization of lts area.
From the foregoing it will be appreciated that the present invention is effective in vie~ of the utilization of semiconductor wafers.
As abo~e described in conjunction with Figure 2, the present invention has tbe structural feature that the base layer to which the control gate 24 i9 attached that is to say, the base layer 14 of the first transistor 12-14-16 is thick as compared with the prior art practice. Therefore the first transistor has a low current amplification factor and a control current -Ic for turning the device off approximate~ the principal current I to be turned off.
That i9~ a turn off current gain has a value approximating one.
The structural feature as above described is of great advantage to cause gate turn-off thyri~tors to withstand higher voltages. This is because the characteristics of gate turn-off thyristors are most a~fected by the cbaracteristics of the transistor including a control electrode.
~ ore specifically, tbe collector-to emitter : ,. .: , , ., :.. . .
~ ,. - - ~ .
.. . ..

~087321~

g g CED(sus) P g transistors off depends upon a current amplification factor ~ iD the cDmmon emitter configuration within the operating region with low currents. It is well known that the relationship VCEo(sus) = VC~0 / n where VCB0 designates a collector-to-base breakdown voltage upon opening the emitter and n has a value ranging from two (2) to six (6J.
In conventional power transistors, the current amplification factor h ~ in the common ~mitter configuration has been of a value ranging from twenty (20) to thirty (30) within the operating range with low currents, in which the field effect developed in the base region thereof does not decrease the current amplification factor. Thus the substaining voltage VcE0(sus) has been equal to from about one half to one quarter the breakdown voltage YCBo. In other words9 the sustaining voltage VCE0( ) actually withstood by such power transistors has been equal to from about one half to about one quarter the voltage VC~0 withstood by tbe semioonductor diode alone formed of the collector and base regions of such transistors. Accordingly a voltage to be controlled has been inevitable to become relatively lo~.
The relationship as above described is equally applicable to both conventional gate turn-off transistors such as shown in Figure 1 and transistors including, as the base regicn, the semiconductor layer 16 to which a gate electrode i9 attached as shown in Figure 1. Thus the cynamic withstanding voltage has been equ~l to aoout one half the breakdown voltage of the junction J2 alone for the following reasons:
In conventional gate turn-off thyristors it has been of the most importance in view of the design to increase the current control gain provided by the gate electrode, ahd therefore transistors including, as the base region, the semiconductor layer 16 has been high in current amplification f~ctor -FF in the common emitter ¢onfiguration In contrast, the gate turn-off thyristDr of the present invention has a current amplificatiDn factor ~ in the common emitter configuration decreased by about one order of magnitude as compared with conventional ones within the operating range with low and medium currents tin which the field effect developed in the base region is disabled).
That is, the current amplification fa¢tor h has a value not greater than two (2). This results in a sharp increase in the sustaining voltage VCEo(sus) of first transistor part as compared with conventional gate turn-off thyristors having the not smaller than twenty (20). Thu~ the sustaini~g voltage V9uS of this four layer device in the turn-off process is equal to from eight to nine tenths the breakdow~ voltage BV of secDnd PN ~unction J2~
In otber words, the d~namic withstanding voltage i9 greatly decreased to permit control of higher voltage as shown in Figure 6 wherein the principal current I is plotted in ordinate ~0~7320 against a voltage across the first a~d second main electrode in abscissa. Also the arrow indicates the turn-off process through whlch the device is switched from its ON to its OFF state.
According to the present invention, the hFF
can readily be made equal to or less than two (2) because the base layer 14 of the first transistor 12-14-16 is made relatively thick. In addition, rate of carrier injection from the first semiconductor layer 12 is reduced by decreasing the sheet resistance r of that semiconductor lqyer 14a forming one part of the base layer 14, Therefore to decrease the -FF
is further facilitated. Such a decrease in -FF causes a reduction in turn-off current gain, However the semiconductor layer 14a directly contacted by the first semiconductor layer 12 has its sheet resistance made low to permit a decrease in reverse voltage -YCA applied across the first and second semiconductor layers 12 and 1~ respectively upon the turning off. Further the decrease in h causes an increARe in turn-off speed. Therefore an electrical energy required for controlling the turn-off is not high as compared with the prior art practice.
As above described, a decrease in turn-off current gain causes an increase in turn-off control ourrent I but a voltage Vsus capable of being turned off is decreased while a turn-off time is decreased.
This means that the present invention ratber increases a turn-off power gain ln term~ of the mean power, , . . .
.

~387320 As above described, the gate turn-off thrristors of the present invention can withstand higher voltages by decreasing the current amplification factor _FF of the transistor including~ as the ba~e layer, the second semiconductor layer 14 for the common emitter configuration. It will readilg be understood that, in this respect, the present invention increases the ability to control switching devices for controlling high powers.
From the foregoing it i9 seen that the pre~ent invention can readily improve the turn-off characteristics by attaching the ¢ontrol electrode 2~ to the second semiconductor l~yer 1~ thicker than the third semiconductor layer 16. The turn-off characteristics can be further improved by directly contacting the f~rst semiconductor layer 12 with the low resistivity layer 14a forming one part of the second semiconductor layer 14. Further, the arrangement as shown in Figure 5A or 5B has the more improved turn-off characteristlcs because a semiconductor diode including one portlon of the second junction J2 is operated to suppress a reverse blocking voltag~ or to reversely conduct the arrangement thereby to increase a permissible thickness of the second semiconductor l~yer and hence the low resictivity layer.
In addition, the arrangement as shown in Figure 3A or 3B can increase the abilit~ to turn ~t off This is because a thin semiconductor layer 30 hi~her in resistivit~ than the first semiconductor layer 12 ~37320 .
is disposed adjacent to the first PN junction Jl thereby to :~
increase a reverse blocking voltage for the first PN junction Jl to permit a turn-off control voltage -VcA.
Also by causing the current amplification factor -FF

of the common emitter transistor including, as the base region, the second semiconductor layer 14 to be equal to or less than two (2), a higher voltage can be controlled as above described.
While the present invention has been illustrated and .
described in conjunction with a few preferred embodiments thereof 10it is to be understood that numerous changes and modifications ~ ~`
may be resorted without departing from the spirit and scope of the present invention.
`'''~

,, ! ~

;20

Claims (5)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. A semiconductor gate turn-off switching device comprising a semiconductor substrate including a pair of opposed main faces, a first semiconductor layer having a first conductivity type and having a first surface exposed to a first one of said main faces of said semiconductor substrate, a second semiconductor layer having a second conductivity type, having a second surface exposed to said first main face of said semi-conductor substrate and forming a first PN junction with said first semiconductor layer, and-means for applying a reverse voltage across said first PN junction, a third semiconductor layer having a first conductivity type forming a second PN
junction with said second semiconductor layer, and a fourth semiconductor layer having a second conductivity type, having a third surface exposed to a second one of said main faces of said semiconductor substrate and forming a third PN junction with said third semiconductor layer, a first main electrode disposed in ohmic contact with said first surface of said first semiconductor layer, and a second main electrode disposed in ohmic contact with said third surface of said fourth semiconductor layer, and a control electrode disposed in ohmic contact with said second surface of said second semiconductor layer, wherein said second semiconductor layer is thicker than said third semiconductor layer.

2. A semiconductor switching device as claimed in claim 1, wherein said second semiconductor layer is formed of a low resistivity semiconductor layer and a high resistivity semiconductor layer, said low resistivity semiconductor layer including said second surface exposed to said first main face of said semiconductor substrate and connected to said control electrode, and said low resistivity semiconductor layer is interposed between said first semiconductor layer and said high resistivity layer.

3. A semiconductor switching device as claimed in claim 2, wherein said first main electrode is also disposed in ohmic contact with at least a portion of said second surface of said second semiconductor layer exposed to said first main face and said third semiconductor layer includes one portion having a fourth surface exposed to said second main face and connected to the second main electrode.

4. A semiconductor switching device as claimed in claim 1, wherein a semiconductor layer higher in resistivity than said exposed portion of said first semiconductor layer is disposed adjacent said first PN junction at the interface between said first semiconductor layer and said second semi-conductor layer.

5. A semiconductor switching device as claimed in claim 4, wherein there is provided means for applying a reverse voltage across said first PN junction.