CA1018663A - Data processing system having an improved overlap instruction fetch and instruction execution feature - Google Patents

Data processing system having an improved overlap instruction fetch and instruction execution feature

Info

Publication number
CA1018663A
CA1018663A CA186,233A CA186233A CA1018663A CA 1018663 A CA1018663 A CA 1018663A CA 186233 A CA186233 A CA 186233A CA 1018663 A CA1018663 A CA 1018663A
Authority
CA
Canada
Prior art keywords
data processing
processing system
instruction
execution feature
instruction execution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA186,233A
Other languages
English (en)
Other versions
CA186233S (en
Inventor
David D. Devoy
Richard A. Lemay
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Inc
Original Assignee
Honeywell Information Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Information Systems Inc filed Critical Honeywell Information Systems Inc
Application granted granted Critical
Publication of CA1018663A publication Critical patent/CA1018663A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Digital Computer Display Output (AREA)
CA186,233A 1973-01-11 1973-11-20 Data processing system having an improved overlap instruction fetch and instruction execution feature Expired CA1018663A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US00322806A US3811114A (en) 1973-01-11 1973-01-11 Data processing system having an improved overlap instruction fetch and instruction execution feature

Publications (1)

Publication Number Publication Date
CA1018663A true CA1018663A (en) 1977-10-04

Family

ID=23256499

Family Applications (1)

Application Number Title Priority Date Filing Date
CA186,233A Expired CA1018663A (en) 1973-01-11 1973-11-20 Data processing system having an improved overlap instruction fetch and instruction execution feature

Country Status (7)

Country Link
US (1) US3811114A (US20090163788A1-20090625-C00002.png)
JP (1) JPS49105428A (US20090163788A1-20090625-C00002.png)
CA (1) CA1018663A (US20090163788A1-20090625-C00002.png)
DE (1) DE2401364A1 (US20090163788A1-20090625-C00002.png)
FR (1) FR2325304A7 (US20090163788A1-20090625-C00002.png)
GB (1) GB1446569A (US20090163788A1-20090625-C00002.png)
IT (1) IT1008108B (US20090163788A1-20090625-C00002.png)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1059639A (en) * 1975-03-26 1979-07-31 Garvin W. Patterson Instruction look ahead having prefetch concurrency and pipe line features
US4042914A (en) * 1976-05-17 1977-08-16 Honeywell Information Systems Inc. Microprogrammed control of foreign processor control functions
US4210960A (en) * 1977-09-02 1980-07-01 Sperry Corporation Digital computer with overlapped operation utilizing conditional control to minimize time losses
US4255785A (en) * 1978-09-25 1981-03-10 Motorola, Inc. Microprocessor having instruction fetch and execution overlap
US4298927A (en) * 1978-10-23 1981-11-03 International Business Machines Corporation Computer instruction prefetch circuit
US4360868A (en) * 1978-12-06 1982-11-23 Data General Corporation Instruction prefetch means having first and second register for storing and providing a current PC while generating a next PC
US4253147A (en) * 1979-04-09 1981-02-24 Rockwell International Corporation Memory unit with pipelined cycle of operations
US4296470A (en) * 1979-06-21 1981-10-20 International Business Machines Corp. Link register storage and restore system for use in an instruction pre-fetch micro-processor interrupt system
US4279016A (en) * 1979-06-21 1981-07-14 International Business Machines Corporation Instruction pre-fetch microprocessor interrupt system
US4455606A (en) * 1981-09-14 1984-06-19 Honeywell Information Systems Inc. Logic control system for efficient memory to CPU transfers
US5278960A (en) * 1989-08-16 1994-01-11 Nec Corporation Information processing apparatus having detecting means for operand overlaps
US5325490A (en) * 1991-12-18 1994-06-28 Intel Corporation Method and apparatus for replacement of an original microprocessor with a replacement microprocessor in a computer system having a numeric processor extension
JP3182591B2 (ja) * 1993-01-20 2001-07-03 株式会社日立製作所 マイクロプロセッサ
GB2282474B (en) * 1993-09-30 1998-02-25 Intel Corp Buffer memory management for a computer network node
US7149878B1 (en) * 2000-10-30 2006-12-12 Mips Technologies, Inc. Changing instruction set architecture mode by comparison of current instruction execution address with boundary address register values
US7711926B2 (en) * 2001-04-18 2010-05-04 Mips Technologies, Inc. Mapping system and method for instruction set processing
US6826681B2 (en) * 2001-06-18 2004-11-30 Mips Technologies, Inc. Instruction specified register value saving in allocated caller stack or not yet allocated callee stack
US7107439B2 (en) * 2001-08-10 2006-09-12 Mips Technologies, Inc. System and method of controlling software decompression through exceptions

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL276236A (US20090163788A1-20090625-C00002.png) * 1961-03-24
DE1187044B (US20090163788A1-20090625-C00002.png) * 1961-09-13 1965-02-11
BE626951A (US20090163788A1-20090625-C00002.png) * 1962-01-22
US3533077A (en) * 1967-11-08 1970-10-06 Ibm Address modification
CA1013861A (en) * 1972-10-10 1977-07-12 Adrianus J. Van De Goor Special instruction processor

Also Published As

Publication number Publication date
IT1008108B (it) 1976-11-10
JPS49105428A (US20090163788A1-20090625-C00002.png) 1974-10-05
DE2401364A1 (de) 1974-07-18
US3811114A (en) 1974-05-14
GB1446569A (US20090163788A1-20090625-C00002.png) 1976-08-18
FR2325304A7 (fr) 1977-04-15

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