BRPI0822705A2 - Painel de ligações impresso e método para fabricar o mesmo - Google Patents
Painel de ligações impresso e método para fabricar o mesmoInfo
- Publication number
- BRPI0822705A2 BRPI0822705A2 BRPI0822705-5A BRPI0822705A BRPI0822705A2 BR PI0822705 A2 BRPI0822705 A2 BR PI0822705A2 BR PI0822705 A BRPI0822705 A BR PI0822705A BR PI0822705 A2 BRPI0822705 A2 BR PI0822705A2
- Authority
- BR
- Brazil
- Prior art keywords
- manufacturing
- same
- patch panel
- printed patch
- printed
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000000034 method Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/142—Arrangements of planar printed circuit boards in the same plane, e.g. auxiliary printed circuit insert mounted in a main printed circuit
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4688—Composite multilayer circuits, i.e. comprising insulating layers having different properties
- H05K3/4694—Partitioned multilayer circuits having adjacent regions with different properties, e.g. by adding or inserting locally circuit layers having a higher circuit density
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01023—Vanadium [V]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01087—Francium [Fr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0183—Dielectric layers
- H05K2201/0187—Dielectric layers with regions of different dielectrics in the same layer, e.g. in a printed capacitor for locally changing the dielectric properties
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09536—Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10431—Details of mounted components
- H05K2201/10439—Position of a single component
- H05K2201/10484—Obliquely mounted
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49126—Assembling bases
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US7179008P | 2008-05-19 | 2008-05-19 | |
PCT/JP2008/073344 WO2009141928A1 (ja) | 2008-05-19 | 2008-12-22 | プリント配線板及びその製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
BRPI0822705A2 true BRPI0822705A2 (pt) | 2015-07-07 |
Family
ID=41315060
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
BRPI0822705-5A BRPI0822705A2 (pt) | 2008-05-19 | 2008-12-22 | Painel de ligações impresso e método para fabricar o mesmo |
Country Status (8)
Country | Link |
---|---|
US (2) | US8431829B2 (pt) |
EP (1) | EP2280594A4 (pt) |
JP (1) | JPWO2009141928A1 (pt) |
KR (1) | KR101198061B1 (pt) |
CN (1) | CN102037796A (pt) |
BR (1) | BRPI0822705A2 (pt) |
TW (1) | TW201004499A (pt) |
WO (1) | WO2009141928A1 (pt) |
Families Citing this family (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7982135B2 (en) * | 2006-10-30 | 2011-07-19 | Ibiden Co., Ltd. | Flex-rigid wiring board and method of manufacturing the same |
US8400782B2 (en) | 2009-07-24 | 2013-03-19 | Ibiden Co., Ltd. | Wiring board and method for manufacturing the same |
JP2011119616A (ja) * | 2009-12-07 | 2011-06-16 | Fujitsu Ltd | プリント配線基板の製造方法、プリント配線基板、および電子装置 |
CN102771200A (zh) * | 2010-02-22 | 2012-11-07 | 三洋电机株式会社 | 多层印刷电路板及其制造方法 |
CN102548253B (zh) * | 2010-12-28 | 2013-11-06 | 富葵精密组件(深圳)有限公司 | 多层电路板的制作方法 |
WO2012089275A1 (en) | 2010-12-30 | 2012-07-05 | Option Wireless Limited | Multi board module with implant |
KR101789237B1 (ko) * | 2011-01-19 | 2017-10-24 | 삼성디스플레이 주식회사 | 액정 표시 장치 |
DE102011051411A1 (de) * | 2011-06-28 | 2013-01-03 | Schweizer Electronic Ag | Prepreg, Verfahren zum Herstellen eines Prepregs, Verfahren zum Herstellen eines Leiterplattenelements sowie Leiterplattenelement |
US20130025914A1 (en) * | 2011-07-25 | 2013-01-31 | Ibiden Co., Ltd. | Wiring board and method for manufacturing the same |
FR2985367A1 (fr) * | 2011-12-29 | 2013-07-05 | 3D Plus | Procede de fabrication collective de modules electroniques 3d ne comportant que des pcbs valides |
JP5406322B2 (ja) * | 2012-03-01 | 2014-02-05 | 株式会社フジクラ | 電子部品内蔵多層配線基板及びその製造方法 |
JP5261756B1 (ja) * | 2012-03-30 | 2013-08-14 | 株式会社フジクラ | 多層配線基板 |
TWI465163B (zh) * | 2012-04-20 | 2014-12-11 | Bridge Semiconductor Corp | 具有內建加強層之凹穴基板及其製造方法 |
WO2013168539A1 (ja) * | 2012-05-09 | 2013-11-14 | 株式会社村田製作所 | 樹脂多層基板およびその製造方法 |
US20130337648A1 (en) * | 2012-06-14 | 2013-12-19 | Bridge Semiconductor Corporation | Method of making cavity substrate with built-in stiffener and cavity |
JP6082233B2 (ja) * | 2012-10-31 | 2017-02-15 | イビデン株式会社 | 配線板及びその製造方法 |
FR3001602B1 (fr) | 2013-01-25 | 2021-05-14 | Thales Sa | Procede de fabrication d'un circuit imprime |
JP6160308B2 (ja) * | 2013-07-02 | 2017-07-12 | 富士通株式会社 | 積層基板 |
CN205213161U (zh) | 2013-09-06 | 2016-05-04 | 株式会社村田制作所 | 多层基板 |
US9433077B2 (en) * | 2014-02-14 | 2016-08-30 | International Business Machines Corporation | Substrate device and electric circuit arrangement having first substrate section perpendicular to second substrate section |
US9351410B2 (en) | 2014-03-07 | 2016-05-24 | Fujikura Ltd. | Electronic component built-in multi-layer wiring board and method of manufacturing the same |
US9699921B2 (en) | 2014-08-01 | 2017-07-04 | Fujikura Ltd. | Multi-layer wiring board |
CN105657971B (zh) * | 2014-11-14 | 2018-11-20 | 欣兴电子股份有限公司 | 内埋式元件封装结构及其制作方法 |
KR102163039B1 (ko) * | 2015-04-07 | 2020-10-08 | 삼성전기주식회사 | 인쇄회로기판, 그 제조방법, 및 전자부품 모듈 |
US10098241B2 (en) | 2015-10-23 | 2018-10-09 | International Business Machines Corporation | Printed circuit board with edge soldering for high-density packages and assemblies |
JP2017123459A (ja) * | 2016-01-08 | 2017-07-13 | サムソン エレクトロ−メカニックス カンパニーリミテッド. | プリント回路基板 |
JP7096992B2 (ja) * | 2017-10-31 | 2022-07-07 | 大日本印刷株式会社 | 貫通電極基板及び実装基板 |
CN110278657B (zh) * | 2018-03-16 | 2022-05-27 | 宏启胜精密电子(秦皇岛)有限公司 | 复合电路板及其制造方法 |
US11178772B2 (en) * | 2018-03-29 | 2021-11-16 | At&S Austria Technologie & Systemtechnik Aktiengesellschaft | Component carrier connected with a separate tilted component carrier for short electric connection |
CN116075074A (zh) * | 2021-11-02 | 2023-05-05 | 宏启胜精密电子(秦皇岛)有限公司 | 电路板及其制造方法 |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5081563A (en) * | 1990-04-27 | 1992-01-14 | International Business Machines Corporation | Multi-layer package incorporating a recessed cavity for a semiconductor chip |
JPH11317582A (ja) * | 1998-02-16 | 1999-11-16 | Matsushita Electric Ind Co Ltd | 多層配線基板およびその製造方法 |
US6281446B1 (en) * | 1998-02-16 | 2001-08-28 | Matsushita Electric Industrial Co., Ltd. | Multi-layered circuit board and method of manufacturing the same |
JP2000165007A (ja) | 1998-11-27 | 2000-06-16 | Nec Corp | プリント配線板、電子部品及び電子部品の実装方法 |
JP3795270B2 (ja) | 1999-09-10 | 2006-07-12 | 大日本印刷株式会社 | 多層プリント配線基板製造方法及び多層プリント配線基板 |
US6459046B1 (en) * | 2000-08-28 | 2002-10-01 | Matsushita Electric Industrial Co., Ltd. | Printed circuit board and method for producing the same |
JP4166532B2 (ja) * | 2002-08-27 | 2008-10-15 | 大日本印刷株式会社 | プリント配線板の製造方法 |
JP2005045150A (ja) * | 2003-07-25 | 2005-02-17 | Matsushita Electric Ind Co Ltd | 中間接続用配線基材および多層配線基板、ならびにこれらの製造方法 |
TWI246375B (en) * | 2004-05-06 | 2005-12-21 | Siliconware Precision Industries Co Ltd | Circuit board with quality-identified mark and method for identifying the quality of circuit board |
JP2006024744A (ja) * | 2004-07-08 | 2006-01-26 | Renesas Technology Corp | 半導体装置および半導体装置の製造方法 |
TWI414218B (zh) * | 2005-02-09 | 2013-11-01 | Ngk Spark Plug Co | 配線基板及配線基板內建用之電容器 |
JP4880277B2 (ja) * | 2005-10-06 | 2012-02-22 | 日本特殊陶業株式会社 | 配線基板の製造方法 |
US8071883B2 (en) | 2006-10-23 | 2011-12-06 | Ibiden Co., Ltd. | Flex-rigid wiring board including flexible substrate and non-flexible substrate and method of manufacturing the same |
EP2434848A1 (en) | 2006-10-24 | 2012-03-28 | Ibiden Co., Ltd. | Flex-rigid wiring board and method of manufacturing the same |
TWI339880B (en) | 2007-05-31 | 2011-04-01 | Unimicron Technology Corp | Structure of pachaging substrate and package structure thereof having chip embedded therein |
CN102037797B (zh) | 2008-05-23 | 2013-11-06 | 揖斐电株式会社 | 印刷电路板及其制造方法 |
-
2008
- 2008-12-22 WO PCT/JP2008/073344 patent/WO2009141928A1/ja active Application Filing
- 2008-12-22 EP EP08874395A patent/EP2280594A4/en not_active Withdrawn
- 2008-12-22 BR BRPI0822705-5A patent/BRPI0822705A2/pt not_active IP Right Cessation
- 2008-12-22 KR KR1020107017159A patent/KR101198061B1/ko active IP Right Grant
- 2008-12-22 CN CN2008801293375A patent/CN102037796A/zh active Pending
- 2008-12-22 JP JP2010512906A patent/JPWO2009141928A1/ja active Pending
- 2008-12-29 TW TW097151252A patent/TW201004499A/zh unknown
-
2009
- 2009-05-18 US US12/453,632 patent/US8431829B2/en active Active
-
2013
- 2013-03-28 US US13/852,233 patent/US9029713B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US8431829B2 (en) | 2013-04-30 |
TW201004499A (en) | 2010-01-16 |
WO2009141928A1 (ja) | 2009-11-26 |
US20130213694A1 (en) | 2013-08-22 |
EP2280594A4 (en) | 2012-06-27 |
CN102037796A (zh) | 2011-04-27 |
US20090283312A1 (en) | 2009-11-19 |
KR101198061B1 (ko) | 2012-11-07 |
KR20100102193A (ko) | 2010-09-20 |
JPWO2009141928A1 (ja) | 2011-09-29 |
US9029713B2 (en) | 2015-05-12 |
EP2280594A1 (en) | 2011-02-02 |
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