BR102013030006B1 - CIRCUIT ARCHITECTURE FOR CHANNEL ESTIMATION AND DISTORTION COMPENSATION IN PHYSICAL CHANNELS OF LTE AND LTE-ADVANCED NETWORK UPLINK - Google Patents

Abstract

circuit architecture for channel estimation and distortion compensation in physical uplink channels of lte and lte-advanced networks, consisting of a pipeline structure and multiple clock domain sections which include at least a first section, with clk1 clock, spectral adjustment and sc-fdma frame structure processing, a second section, with clk2 clock, channel estimation, noise estimation and noise compensation and iq unbalance, a third section, with clk3 clock, decoder channels and harq process management, with the exchange of messages and commands with the upper layers of the radio protocol stack performed by a fourth section, with clock clk4, further comprising modules (106) specialized in the interface between said domain sections clock through associated memory devices (110).

Description

APPLICATION FIELD

The present invention applies to the field of Telecommunications, more specifically to Hardware Engineering, with regard to LTE and LTE-Advanced type networks. More specifically, it proposes an integrated circuit architecture for channel estimation and distortion compensation in physical uplink channels of LTE and LTE-Advanced networks.

The invention takes into account in the receiver architecture the large multiplicity of UEs that can transmit in the uplink in the same TTI (Time Transmission Interval). The proposed architecture is suitable, but not limited, for implementation in devices that employ Hardware Description Language (HDL) as part of the design process. An example of such devices are the FPGA and ASIC. The architecture proposed in this work was validated and tested in an FPGA device. However, nothing prevents the architecture from being adapted for implementation in DSP (Digital Signal Processor) devices.

TECHNICAL STATUS

For a better understanding of the descriptive report, some terms and acronyms used in it are presented below:

ASIC (Application Specific Integrated Circuit) - Application Specific Integrated Circuit; it is an integrated circuit built to perform a specific task, that is, customized for a particular use as opposed to general purpose ICs.

ASIP (Application-Specific Instruction Set Processor) - Application-Specific Instruction Set Processor; is an integrated circuit component for the execution of specific functionalities that is used in the design of SoC (System on a Chip) type devices. The SoC makes it possible to further compact equipment by increasing the level of integration of complete systems on a single chip, for example, in addition to the general-purpose processor, specific features that would typically be external to the chip, such as video processing, can also be included. network and wireless interfaces, among other features.

CDMA (Code Division Multiple Access) - is a multiple access scheme that employs multiplexing of user data spread in frequency by code.

DFT-OFDMA (Discrete Fourier Transform - Orthogonal Frequency Division Multiple Access) - is a multiple user access scheme that employs multiplexing by orthogonal subcarriers. This scheme differs from the traditional OFDMA in that it does not directly multiplex the user data, but the DFT transform of the user data.

DMRS (Demodulation Reference Signals) - consists of reference signals used to help estimate the transmission channel.

DSP (Digital Signal Processor) - consists of a dedicated processor for digital signal processing.

FPGA (Field Programmable Gate Array) - Field Programmable Gate Array, consists of a large array of logic cells or configurable logic blocks contained in a single integrated circuit. Each cell contains computational capacity to implement logic functions and perform routing for communication between them. 3GPP (3rd Generation Partnership Project) - Entity that brings together six telecommunications standards development organizations (ARIB, ATIS, CCSA, ETSI, TTA, TTC) to generate reports and specifications that define 3GPP technology in the areas of: radio access (RAN), service and system aspects (SA), core network and terminals (CT) and GSM EDGE radio access networks (GERAN). The TS 36.212 standard refers to Multiplexing and Channel Coding in Universal Terrestrial Access via Evolved Radio (E-UTRA) systems.

HARQ (Hybrid Automatic Repeat Request) - is a hybrid scheme of automatic retransmission request in case of error and channel decoding, where message retransmissions or incremental bit transmissions are performed in order to increase the performance of channel decoding for correction of transmission errors.

HDL (Hardware Description Language) - consists of a hardware description language that makes it possible to model digital circuits to be synthesized in a later stage, through automatic synthesis tools.

LTE (Long Term Evolution) - standard for mobile communication networks that is being adapted by operators using GSM technologies, such as 3G/W-CDMA and HSPA, and also by CDMA operators. This new radio technology allows speeds of up to 100 Mbit/s downlink and 50 Mbit/s uplink (maximum rates).

LTE-Advanced or LTE-A - Consists of a version later than LTE that must allow communication rates in the uplink and downlink higher than 1 Gbit/s.

OFDM (Orthogonal Frequency Division Multiplexing) - consists of a modulation scheme that employs multiple orthogonal carriers through an efficient Fast Fourier Transform (FFT) algorithm.

OFDMA (Orthogonal Frequency Division Multiple Access) - it is the use of OFDM to provide multiple access through allocation of distinct blocks of subcarriers and OFDM symbols for multiple users.

PAPR (Peak-to-Avarage Power Ratio) - is a measure of the ratio between the peak power and the average power of the signal.

PUCCH (Physical Uplink Control Channel) - is the physical channel responsible for transmitting channel link quality measurements, requests for scheduling transmissions from the terminal and ACK/NACK confirmation of correct reception of transmissions on the downlink.

PUSCH (Physical Uplink Shared Channel) - is the physical channel responsible for transmitting user data, in addition to the same measurements and confirmations transmitted on the PUCCH.

RB (Resource Block) - is a set of data transmission resources that is defined in a block of 12 subcarriers over a 0.5 ms time slot, ie 6 or 7 OFDM symbols according to the format of used frame. SC-FDMA (Single Carrier-Frequency Division Multiple Access) - is a frequency multiple access scheme that preserves the low PAPR properties of single carrier signal transmissions in OFDM transmission schemes. TTI (Transmission Time Interval) - Time interval that contains data that is processed independently of other intervals. In LTE a TTI is a subframe that equals 1 millisecond. UE (User Equipment) - is the user's access terminal. WCDMA - is the broadband version of CDMA.

The cellular mobile communication LTE network was developed and standardized in the context of the 3GPP forum to meet the growing demand for broadband data traffic and real-time interactive applications on mobile networks. The technologies proposed for the LTE network present significant evolutions when compared to the technologies of the CDMA and WCDMA networks derived from the third generation (3G) of the cellular network, especially with regard to the air interface.

The LTE air interface breaks the spread-spectrum code multiplexing model in favor of narrowband orthogonal subcarrier multiplexing technology. There were significant benefits in terms of spectral efficiency and optimization of spectrum usage for broadband signals. Multiple allocation of users in both temporal and spectral dimensions becomes possible, with the benefit of having a more efficient and significantly greater allocation of active users.

The use of multiple orthogonal subcarriers and the addition of a cyclic prefix from the temporal samples of the signal simplify the methods of equalization of the received signal. This is a consequence of the fact that the equalization is performed by a narrowband subcarrier, which makes it possible to consider the distortions coming from the transmission channel as linear. In this way, the equalization process simply consists of adjusting the gain and phase rotation of each subcarrier.

In the uplink, the LTE multiple access scheme employs multiple orthogonal narrowband carriers, but the signals coming from the UEs (User Equipments) are inherently single-carrier. The UE single-carrier signal is transformed to the frequency domain and mapped to consecutive sub-carriers. In this way, it becomes possible to perform the equalization of the received signal in the frequency domain with the same simplicity of an OFDM signal. The limitation of using only consecutive subcarriers limits flexible use and, therefore, more efficient use of spectrum. On the other hand, the signal to be transmitted now has the characteristics of a single carrier signal, without the high PAPR (Peak-to-Average Power Ratio) problems, common in OFDMA signals. This feature makes it possible to use power amplifiers with a smaller linear pitch in the UE. This is important to reduce the UE's power consumption and therefore increase battery life.

LTE-A makes the SC-FDMA multiple access technique more flexible to allow segmented use of spectrum, that is, groups of non-contiguous subcarriers. This multiple access technique is called DFT-OFDMA and also employs the DFT transform on the signal before frequency mapping. One difference is the possibility of mapping more than one transformed signal to groups of non-contiguous subcarriers in frequency. In this way, it is possible, for example, for the UE to transmit the physical channels PUSCH and PUCCH simultaneously.

If only a single group of subcarriers is used by the UE, DFT-OFDMA becomes equivalent to SC-FDMA. This guarantees LTE-A compatibility with LTE. Furthermore, this is the scenario where the lowest crest factor (PAPR) in the signal is achieved. There is a trade-off between PAPR and spectral efficiency when using multiple non-contiguous groups of subcarriers in DFT-OFDMA.

In OFDM systems, the equalization process used in signal detection consists of linearly correcting the amplitude and phase of each signal subcarrier. This correction is possible based on the channel estimation performed on specific subcarriers, which carry reference signals previously known by the receiver, called DMRS (Demodulation Reference Signals). From the channel estimate performed on the subcarriers that carry DMRS, it is possible to extrapolate and interpolate these estimates for the subcarriers that carry data.

The channel estimation in DMRS and the extrapolation and interpolation of this estimate for channel equalization is performed in LTE in a set of Resource Blocks (RBs) per subframe of the SC-FDMA signal. Each RB consists of 12 successive subcarriers in a 0.5ms long slot. A subframe is 1 ms long and consists of two slots. The subframe is the smallest user allocation unit in time, while the RB is the smallest frequency allocation unit. The slot defines the temporal repetition pattern of the reference signal. Depending on the physical channel, a specific configuration for the reference signals is defined. For example, PUSCH in SC-FDMA employs one reference OFDM symbol per slot. In this case, all subcarriers in that token are used as DMRS.

The present invention proposes an efficient architecture for implementing an integrated circuit of equalization processes for LTE and LTE-A systems. However, any equalization process that uses DMRS in a block structure of subcarriers per subframe can use the proposed architecture.

In the known state of the art, the publication US20110280200A1, entitled Hardware implementation of uplink receiver with matched throughput, also published as WO201114333328A1, proposes an architecture for the uplink receiver based on parallel processing cores. This architecture is designed to provide the processing power needed to demodulate and decode the received signal according to the data throughput required by the LTE uplink. The level of parallelization of this architecture is limited, employing some processing cores with multiple instances of IDFT mechanisms to be able to flow the data received by the uplink. This architecture is very suitable for implementations on multicore DSP processing devices, which may also include some dedicated processing circuitry. However, processing in the cores is still inherently sequential. Hence the need for careful design to avoid processing bottlenecks, given the high throughput of LTE in uplink and downlink traffic. Additionally, this architecture may have difficulty supporting future system upgrades to meet the constantly evolving LTE standard.

Publication WO2012030028 A1, entitled Apparatus and method for I/Q offset cancellation in SC-FDMA system, also published as EP2612457A1 and US20130155833, addresses a specific method of IQ offset cancellation, which is one of the distortions that degrade uplink signals . This IQ offset issue typically arises due to eNodeB and UEs RF front-end calibration issues. The publication discloses an apparatus and method for canceling IQ offset in an SC-FDMA system. The described architecture is restricted to using the DMRS of the physical uplink channels to implement the IQ offset cancellation functionality. The following units are used for this purpose: (a) Channel estimation unit by linear interpolation to estimate the channel using symbols demodulation reference (DMRS); (b) A regen/cancel unit to calculate the IQ offset; (c) An offset IQ offset/measurement unit to generate an offset-free VQ signal. However, it does not cover complete reception solutions for the physical uplink channels on an integrated circuit.

When searching for patents dealing with the reception of physical uplink channels, specifically PUSCH and PUCCH, most results refer to methods of channel estimation and signal regeneration.

Thus, for example, patent document US 20110286499 A1 (CA2743442A1, CN102232308A, EP2353317A2, WO2010055420A2, WO2010055420A3) proposes an MMSE channel estimation method with reduced complexity. Patent US 8515376 B2 proposes a method of estimating the MIMO channel transfer functions of multiple UEs transmitting on the uplink. Another example is the document US 20110194633 A1 which also employs a method aimed at channel estimation, but with an appropriate architecture for receiving the PDSCH at the UE, which is a physical downlink channel. The publication US 20070211815 A1, in turn, also describes a specific processing method for the channel decoding section, where a scale factor is calculated to adjust the soft bits (LLR) before the turbo decoding.

The invention proposed herein is not limited to a specific processing method, but aims to reveal an architecture that provides a framework of resources for the efficient implementation of a PUSCH and PUCCH receiver in an integrated circuit, compatible with the required data throughput and latency by 3GPP LTE and LTE-A standard.

OBJECTIVES OF THE INVENTION

In view of the above, it is an object of the invention to provide a circuit architecture that can be used interchangeably for the physical channels PUSCH (Physical Uplink Shared Channel) and PUCCH (Physical Uplink Control Channel), regardless of the mathematical method of equalization and estimation channel that will be implemented.

Another objective is to present an integrated circuit architecture for demultiplexing and compensation of physical uplink channel signal degradations, PUSCH and PUCCH, coming from multiple mobile access units (UE - User Equipment) in LTE and LTE-A networks.

Another objective is to provide a mechanism for demultiplexing user data (transport blocks) and reporting of terminal measurements transmitted by the UE in the PUSCH in accordance with the 3GPP TS36.212 and TS36.211 standards.

Yet another objective of the present invention is to reveal an efficient architecture, aimed at devices that employ configurable logic, such as FPGA, ASIC and ASIP (Application-specific instruction set processor), in order to efficiently distribute the processing load among logic resources to meet time and latency requirements of LTE.

GENERAL DESCRIPTION OF THE INVENTION

The present invention contrasts with the state of the art by using a massively parallel architecture in an assembly-line structure (pipeline), with pertinent clock domains for each processing section: (a) spectral adjustment and processing of the SC- frame structure FDMA per subframe, with cyclic prefix removal and FFT calculation; (b) channel estimation, noise estimation, IQ imbalance compensation, IQ offset compensation, equalization and IDFT; (c) channel decoding and HARQ process management; (d) treatment and generation of messages to higher layers (L2).

Clock domain crossings are performed by specialized modules and typically involve some memory management. For example, the crossing of domain (a) to (b) is performed by a module called Demapper, which is responsible for assembling the time-frequency frame associated with a subframe and for demapping this frame to sequentially provide data for each user sequentially for section (b). [1a] This architecture has the advantage of being scalable, having high processing power and efficiently exploiting the resources of FPGA and ASIC devices.

In contrast to the known technique, [4] IQ offset distortion as well as IQ unbalance and propagation environment fading are compensated in an appropriate Distortion Compensation module 108 and 112. The structure of blocks 108 and 112 constitutes the most important aspect. relevant part of the present invention.

The present invention does not address specific distortion compensation methods, but provides a processing circuit infrastructure, as a resource framework that enables the use of any distortion compensation technique.

In the context of the physical layer receiver architecture, the present invention reveals the design of a component for compensating degradations, which come from the signal propagation medium and imperfections in the signal transmission and reception components. The architecture proposed for this component is based on the premise that there are reference signals available for demodulation (DMRS - Demodulation Reference Signal) and, therefore, there must be a unit responsible for generating this sequence. In addition, this component also considers that the structure of the signal to be processed is SC-FDMA and that there is a unit for estimating degradations and another unit for compensating them.

Still in the context of the receiver's physical layer architecture, this invention reveals control signals and interfaces necessary for the joint operation of the degradation compensation component with the demapping and channel decoding components.

The proposed architecture efficiently distributes the processing load across logic resources to meet LTE time and latency requirements. In the present invention, the level of parallelization of the architecture and the clock sections used make it possible to execute the entire uplink reception chain in the time interval of 1 subframe, which is equivalent to 1 ms.

The present invention also reveals, as an example, results of the implementation of the proposed architecture in FPGA.

One of the characteristic aspects of the present invention is a massively parallel receiver architecture, with pipeline structure and with multiple clock domain sections, designed for embodiments in integrated circuit devices such as FPGA, ASIC and ASIP. This architecture, which is presented in general lines in Figure 1(a), reveals the main components of the receiver, the interactions between them, functionalities and the expected behavior for these components.

DESCRIPTION OF THE FIGURES

Figure 1(a) illustrates the general architecture of the circuit for receiving SC-FDMA signals transmitted in the uplink.

Figure 1(b) illustrates the partitioning of the SC-FDMA receiver circuit architecture by clock domain.

Figure 2 illustrates how the demodulation of SC-FDMA symbols is performed.

Figure 3 illustrates the communication interface of the AXI Stream A data streams that is used in the communication between the receiver components.

Figure 4 shows details of the physical channel mapping component and data streams.

Figure 5 shows how a user's data matrix is serialized in communications from Equalizer 108 to Demapper 106 and Decoder 114, the data streams being comprised of AXI Stream B.

Figure 6 shows details of the Equalizer 108 architecture.

Figure 7 shows the Sequence Diagram A of Component 108 with an emphasis on Component Process 602.

Figure 8 shows the diagram of State Machine A of Controller 902.

Figure 9 shows the structural architecture of Processing Component 602.

Figure 10 shows the B Sequence Diagram of Component 108 with an emphasis on the Channel Estimation Component 604.

Figure 11 shows the diagram of State Machine B of Controller 1202.

Figure 12 shows the structural architecture of channel estimation component 1202.

Figure 13 shows the C Sequence Diagram of Component 108 with an emphasis on Component GenRef 606.

Figure 14 shows the 1502 Controller C State Machine diagram.

Figure 15 shows the structural architecture of the Zadoff-Chu 606 Reference Signal Generation Component.

DETAILED DESCRIPTION OF THE INVENTION

The disclosure of the architecture of the PUCCH and PUSCH receiver is important to provide the operational context in which the aspect of the invention that you want to detail in this patent application is inserted, which are components 108 and 112, used to compensate for distortions generated in the path of the uplink signal.

The higher-level circuit components are shown in Figure 1(a).

Figure 1(b) illustrates a [5] partitioning of circuits by clock domain. Considering the receiver architecture illustrated in these figures, an implementation was performed in FPGA with four clock domains, which is the minimum necessary to implement architecture 100.

[6] Clk1 clock domain is defined for the SC-FDMA 104 demodulation component, which operates at the 30.720 MHz uplink signal sampling rate.

Another [7] clock domain, Clk2, which can be a multiple of 30.720 MHz, is defined for the operation of the compensation components of PUSCH 108 and compensation of PUCCH 112. In the FPGA embodiment, a clock of 61.480 MHz was used. PUSCH 114 channel decoding is performed in a specific clock domain, Clk3, due to processing demands and the need to manage HARQ processes, which are responsible for receiving additional data increments (parity bits) for decoding data transport blocks that were detected with errors (NACK).

The decoding of PUCCH 116 is computationally less complex and can be performed in both the Clk2 clock domain and the Clk3 domain. The Clk4 domain is used to operate the FAPI 118 component, which exchanges messages and commands with the upper layers of the radio protocol stack.

A general description of the highest hierarchy components shown in Figures 1(a) and 1(b) follows.

The interface with the AD (Analog to Digital) converters is performed by the circuit component 102. This component generates two data streams, I and Q, at a constant rate of 30.720 MSa/s, resulting from a sampling with a frequency of 30.720 MHz An example of an embodiment that employs 12 bits of quantization per sample should result in I and Q data streams with a rate of 368.64 Mbps each.

The SC-FDMA demodulation component 104 receives as input the I and Q signal streams defined in the time domain and returns the transformed streams to the frequency domain per SC-FDMA symbol. From this component, all the transfer of signal streams (streaming) is performed by burst, with appropriate signaling according to standard AXI Streaming format. More details about this format will be presented later. Frame synchronization and signaling signals are also used as input to this component. Such signals are necessary for indicating blocks of SC-FDMA symbol samples in symbol processing.

The Demap component 106 is responsible for assembling the data matrix, which is stored at 110 and involves I and Q signal samples per subcarrier and per SC-FDMA symbol, considering as many symbols as necessary to complete a subframe. This component is also responsible for demapping, from this matrix, PUSCH user data streams and PUCCH user reports. Thus, as the data flow source for the PUCCH and PUSCH processing chains, the component 106 is still responsible for triggering the processing and configuration of the subsequent stages 108 and 112 of compensation for the degradations of the propagation medium of the uplink sign.

In the proposed architecture, the subframe data matrix assembly process competes with the process of mapping the signal flows per UE and per physical channel (PUSCH and PUCCH). To avoid data loss, a mechanism called “ping pong” is used, which consists of employing two matrices. While an array is assembled for processing, another array, already assembled, is processed. At each subframe period, the matrices are changed.

The propagation medium degradations are compensated independently for the PUSCH and PUCCH physical channels through the respective components Compens PUSCH 108 and Compens PUCCH 112. The need for distinct components for the PUSCH and PUCCH is due to specificities in the user data multiplexing patterns , which are multiplexed by subcarriers on the PUSCH and by spreading code on the PUCCH. Furthermore, the generation and allocation patterns of reference sequences (DMRS) are also different. Although the components Compens PUSCH 108 and Compens PUCCH 112 employ different methods for generating DMRS, for estimating and for compensating degradations, the architecture for signal processing is similar.

The channel decoding components 114 and 116, particularly the PUSCH decoding 114, implement the decoding according to the 3GPP TS 36.212 standard. The processing of this component 114 starts from the bit reliability (LLR - Log-Likelihood Ratio) estimated internally through the SNR estimated in component 108. Component 114 processes the PUSCH data stream by UE, and returns as possible results the UL-SCH bit transport block and the UE parameter reports called CQI, RI and PMI. The PUCCH decoding component 116 processes data per user that has been spread and demultiplexed by component 112, and can return, per user, the SR (Scheduling Request) parameter and the CQI, RI and PMI parameters. Component CDC/FAPI 118 interfaces with the media access control layer (MAC or L2), which is responsible for controlling the allocation of users in the data matrix 110, modulation level, encoding rate, among other functions. In addition to configuring the PUSCH and PUCCH physical layer receiver per subframe, the MAC Layer (L2) also provides bit transport blocks to be consumed by the downlink transmitter (not described in this invention) and consumes provided bit transport blocks by the uplink receiver. The communication between the receiver 100 and the L2 layer is performed through a specific protocol which, on the receiver 100 side, is performed by the component CDC/FAPI 118 component. This component integrates the synthesis and analysis of messages of the FAPI protocol, it performs clock domain crossovers for 100 component configuration, and implements the physical communication interface which can be Gigabit Ethernet or PCIe.

The PUSCH degradation compensation component 108 was designed according to the structure presented for the receiver in 100. This imposes some design requirements comprising, for example: operating under the clock domain Clk2; provide a configuration interface for the Demapper 106 component; process user streams with latency and time interval less than 1 subframe (1 ms); return, as processing results, user data streams and the respective noise estimates in AXI format compatible with component 114. The present invention describes the compensation of channel degradations, through the estimation, interpolation and linear equalization of the channel. However, the presented architecture can be directly applied to compensate the remaining degradations of a non-ideal calibration of the transmission and reception equipment, which can generate the degradations known as IQ unbalance and IQ translation (IQ offset).

DETAILED DESCRIPTION OF A PREFERRED ACHIEVEMENT

The fulcrum of the present invention is the demodulation subsystem which comprises components 104, 106, 108, 110 and 112, especially component 108 for compensating degradations of the propagation medium of the PUSCH channel.

Compensation of signal transmission and reception degradations, such as those performed by channel fade equalization features, I/Q signal translation and I/Q unbalance, are dealt with in the present invention from the frequency domain, after the demultiplexing the transmitted signal for each UE.

In this case, the dynamics of circuit processing is equivalent to an assembly line (pipeline) that successively processes data from the UEs in the Clk2 Clock Domain:

1. The Demapper component 106 indicates with the NUI (New User Indication) signal to the component 108 that the data transfer of a UE will be performed. In parallel with the NUI signal, configuration parameters are transferred to component 108.

2. Component 108 estimates channel degradations from DMRS stored in 110.

3. The Demapper component 106 reads data from the UE from the data matrix 110 and transfers that data to the component 108 via an AXI Streaming interface.

4. As data is transferred, it is also processed and delivered for channel decoding on an ongoing basis.

The process of [11] demodulation of the SC-FDMA signal, responsible for converting the signal to the frequency domain, is shown in Figure 2. The I/Q data streams, generated at a constant sampling rate of 30.720 MHz by the component 102, are processed continuously by a pipeline structure, following the same pattern applied to the entire architecture. This process can then be segmented from the following components:

• Signaling Component 202 which is responsible for adding an appropriate control signaling for bursts of continuous data streams, consisting of “star” and “valid” signals and synchronized with the expected frame structure;

• Component Remove Cyclic Prefix 204 which is responsible for marking as invalid, through control signaling, the signal samples corresponding to the cyclic prefix of the SC-FDMA signal;

• Spectral Adjustment Component 206 which is responsible for the temporal processing of the half subcarrier frequency deviation that is generated in the transmitter to avoid DC level in the signal;

• FFT Streaming 208 component that performs FFT block transform processing allowing the continuous flow of data in its processing at the cost of only one initial latency.

Figure 3 illustrates the control signaling of the AXI Streaming interface, here called AXI Streaming A, which is used in the communication between the 100 processing components. The bits of the I/Q signal samples of the data stream are concatenated as shown in 302, where the bits of the I signal are mapped to the least significant bits (LSB - Least Significant Bits) of D, and the bits of Q are mapped to the most significant bits (MSB - Most Significant Bits) of D. The subsequent component (Slave) of the processing chain, which consumes the data stream, must signal that it is ready to operate through the TReady 304 signal. The antecedent component (Master) of the chain, which provides the data stream, must provide the TValid 306 signals and TLast 308 in parallel with the data stream of bus TData 310. Signal TValid 306 signals the valid samples of a data burst in TData 310 and Tlast 308 signals the last sample of that same data burst.

The continuous data stream generated by the FFT Streaming Component 208 is consumed by the Demapper Component 106, still in the Clk1 clock domain, to assemble the time-frequency data matrix 110 of a subframe, and containing a number of subcarriers proportional to the bandwidth of the sign.

Figure 4 reveals the highest hierarchical level architecture for the Demapper 106 and Ping-Pong 110 Memory components. These structures provide the mechanism for crossing between the Clk1 and Clk2 clock domains without data loss. The component 402 of the Demapper 106 is responsible for consuming the I/Q data stream and assembling in memory the data matrix, which will be used for demultiplexing the PUSCH and PUCCH physical channels and the data coming from multiple UEs multiplexed on these physical channels. On the other hand, the 404 component operates in the Clk2 clock domain and performs the reading of the data matrix referring to the allocation of a UE in the PUSCH in a continuous set of subcarriers. It is important to point out, however, that the data matrices in which the 402 and 404 components act contain UE allocation data from distinct, albeit subsequent, subframes.

Component 110 is responsible for maintaining data array pairs 406 and 410 of subsequent subframes. This component 110 operates in synch with the 402 and 404 components of the Demapper 106, so that it is transparent to 402 and 404 which is the working matrix. The 404 component always works on the 406 matrix that was filled in the previous subframe by the 402 component. The current subframe is always processed by the 402 component in order to fill the 410 data matrix.

Switching between matrices 406 and 410 is performed by the mechanism developed in 414. Components 402 and 404 do not have direct access to the read and write ports of the memories that store the matrices 406 and 410, but to the ports that are made available by the mechanism. switching 414. With each new subframe, which occurs every 1 ms, the switching mechanism 414 internally switches access to the memories. Thus, when a subframe is terminated, the memory 410 filled by the component 402 becomes accessed by the component 404, while the memory 406 that was processed by the component 404 is now filled by the component 402.

For the sake of simplicity, the time-frequency data matrix has been divided into one part to store the SC-FDMA data symbols, and another part to store the DMRS. The DMRS consist of two SC-FDMA symbols and are represented by the 408 and 412 ping-pong memory arrays, with the 416 switching mechanism operating in the same way as the 414 mechanism. The difference is that the access to the 408 array is filled with the DMRS samples are made available to read and write ports that are connected to component 108. This strategy was adopted so that the same memory that stores the DMRS sequences can be used to store the channel estimate. This procedure optimizes memory usage and saves hardware resources.

As mentioned, Demapper 106 is responsible for configuring and triggering the processing chains (pipeline chains) of components 108 and 112. The configuration is performed through NUI (New User Indication) signaling which is a pulse used to load configuration parameters available on a specific bus for that function. After component configuration, data transfer follows the AXI Streaming interface shown in Figure 5, here called AXI Stream B. User data (UE) corresponds to a subset of 502 rows of the data matrix that are serialized as indicated in 512. The interface control flags are indicated by 506, 508 and 510. Serial data transfer 512 can be performed only after component 108 and 112 signal with TReady 506 at high level. The data is then transferred in burst with the valid samples indicated by TValid signaling 508 and the last sample of the UE data burst indicated by the pulse on the TLast line 510. The format of the D data bus 504 follows the same structure as 302.

Figure 6 shows the breakdown of the top hierarchical level for the Compensator component PUSCH 108, which consists of the following components:

• The Processing component 602 is responsible for processing the UE data stream generated by the Demapper 106. Data compensation is performed based on the channel estimation generated for each sample by the Estimation component 604;

• The 604 Estimation component is responsible for reading the DMRS 408 Mem Memory to perform the channel estimation on the respective DMRS subcarriers. For each DMRS sample there is a channel estimate which is written into the respective DMRS memory location. The channel estimate is performed using as reference the DMRS samples generated locally by the Reference Generation component 606. The channel estimate for the data samples is generated through some interpolation and extrapolation scheme of the estimates obtained for the DMRS;

• The Zadoff-Chu 606 Reference Generation component generates the Zadoff-Chu reference signals according to configuration parameters provided by the Demapper 106;

• The IDFT 608 component also employs an AXI Streaming interface as shown in Figure 5 to process the block discrete Fourier transform on each symbol. The length of the IDFT will depend on how many rows of data matrix 502 are allocated to the user. Each row corresponds to a data subcarrier. The output of the IDFT 608 component employs the same AXI Streaming interface as the input.

Processing Component 602

The operation of the Processing component 602 depends only on the Demapper 106 and Channel Estimation 604 components. The signaling exchange between these components is illustrated in sequence diagram A of Figure 7.

The entire process of equalizing channel degradations starts with a pulse on the NUI (New User Indication) line. For Equalizer 602 the NDFT parameter is also loaded, which provides the size of the IDFT sample block. This parameter indicates the number of rows of the data matrix that will be read and transferred by the Demapper 106. The number of symbols of the data matrix 502 does not need to be loaded, as this parameter is known beforehand from the eNodeB initialization phase. For example, if the frame structure format uses normal cyclic prefix, then the number of SC-FDMA data symbols, excluding the 2 DMRS symbols, will be 12. Otherwise, if the cyclic prefix is of the extended type, then the number of data symbols will be 10.

However, the equalization process will be ready to start only when the EstCh 604 component signals with a pulse on the ChEstDone line. When the Equalizer 602 receives the ChEstDone signal, the TReady line of the input AXI interface rises to the high level (1) and is held at that level until the Demapper transfers all data samples from the UE. The equalizer uses UE Data from Demapper 106 and Channel Estimate Data (ChEstData) from EstCh component 604 which are synchronized through FIFOs and TValid signal before the processing step.

The signaling flow and the user data flow are handled decoupled by component 602. The state machine diagram for signal handling and processing control is shown in Figure 8. The processing structure is partitioned by Controller 902 and by the data processing components involving FIFOs and the data processing module, as illustrated in Figure 9.

Controller State Machine 902 , illustrated in Fig. 8 and here called State Machine A, has a Start state 802 which is typically an operating mode of Controller 902 that resets the entire processing chain of Equalizer 602. operation is driven by reset events (rst) or new subframe signaling (SFI). This is a procedure that synchronizes the Equalizer 602 with subframe events, allowing any error in the component operation dynamics to be detected, without causing the machine to lock up in some wrong state. The E1 error flag signals the occurrence of an SFI out of the expected state.

Likewise, there is an F1 error flag that signals the occurrence of a NUI earlier than expected. NUI and SFI can only occur when the 902 Controller is in Config State. The 804 Configuration State consists of a wait state that is used to keep the operation of the Equalizer 602 synchronized with the Channel Estimator 604 and with the Demapper 106. For example, in normal operation, an EstChDone signal is expected so that there is a change from wait state 804 to processing state 806.

Processing state 806 is the mode of operation in which the equalizer remains until it finishes processing data, which consists of a finite number of cycles equivalent to the number of samples transferred by Demapper 106. For example, for a signal frame structure with normal cyclic prefix, the number of cycles required for data transfer corresponds to NDFT times 10, with one sample being transferred and processed per clock cycle. After this number of cycles, the controller returns to the Config State 804 and remains in this state waiting for the SFI, NUI and EstChDone signals.

604 Channel Estimation Component

The EstCh 604 component is the most complex component out of 108 under the criterion of having the most interactions with other components. The 604 Channel Estimator performs signaling exchange with the Demapper 106, Mem DMRS 408, GenRef 606 and Process (Equalizer) 602 components. The 604 component also performs data exchange through AXI Streaming interfaces (see Figure 3) with the GenRef components 606 and Process 602.

The interaction with the Demapper component 106 is performed due to the need to configure the NDFT parameter of the Channel Estimator for each data sub-matrix 502 of the UEs multiplexed in the PUSCH. It is important to note that component 108 has two independent configuration lines. One line is responsible for configuring the Process 602 component, which will be performed after the EstChDone signal. The other configuration line is routed to the EstCh 604 and GenRef 606 components. These 604 and 606 components must operate and be ready before the 602 component.

Once the EstCh 604 component operation is triggered by the Demapper 106, the EstCh component instructs the GenRef component to generate in real time, with one sample per clock cycle, samples of the Zadoff-Chu reference signal corresponding to two SC-FDMA symbols with NDFT samples each. As reference samples are generated by component 606, component EstCh reads from memory 408 the corresponding sample of DMRS signal, performs channel estimation for the corresponding subcarrier and saves the result in that same memory 408. In parallel, it is calculated also an estimate of the average noise variance for each SC-FDMA symbol.

Once the channel estimation for the DMRS and the noise variance estimation for each of the two DMRS of the subframe is finished, the EstCh 604 component enters the equalization support mode with the signaling of the EstChDone line. When the Process component 602 responds Ready to the Channel Estimator 604, it generates in the AXI interface with the Equalizer 602 an estimate of the coefficient that inverts the channel in the data carrier through the information obtained from the channel in the DMRS, including the estimate of the noise variance. Any channel inversion method, such as MMSE and LSE, can be used, as well as any channel interpolation method.

The structure of component 604 is similar to that of component 602 with regard to decoupling between data and control. In this context, Figure 11 shows the state machine of Controller 1202, here called State Machine B, and Figure 12 the structural architecture of component 604.

The Controller state machine has the Start 1102 and Wait 1104 states equivalent to the 802 and 804 states of the Process component 602. The Equalization State 806 of the Process component is synchronized with the States Estimate Channel 1106, Processing Latency 1108, and Support Equalization 1110 due to the NUI, EstChDone flags and the AXI TLast and TReady interface flags.

The structural architecture of the 604 component is similar to that of the 602 Data Processing component in that Controller 1202 is responsible for generating and handling all control signaling. The 1204 data processing chains have their particularity due to the Delay 1206 Alignment required for synchronization with the Reference Signal Generation component 606. There is also a component for processing noise variance estimation in DMRS.

Reference Generation Component 606

The dependency on other components is lower for the GenRef 606 component. This component only depends on the Demapper 106 for configuration and the EstCh 604 component, which is slave on the AXI interface for the transfer of the generated reference signal.

The EstCh 604 component only needs to signal that it is ready on the TReady line of the AXI interface.

As shown in Figures 14 and 15, the development pattern is the same as for components 602 and 604. The component architecture is structured in Control 1502 and Processing 1504. Controller 1502 handles all control signaling and also records the parameters of configuration, which are the ncs parameter (relating to the cyclical delay of the Zadoff-Chu sequence), and the q parameter (relating to the Zadoff-Chu root), which are defined by the 3GPP TS36.211 standard. The length of the IDFT to be applied for the UE to be processed is also registered in Controller 1502.

The generation of the sequence, performed by the 1504 component, requires the generation of a sample per clock cycle. This requirement leads to a possible realization that uses multiple pipeline stages, which should result in some latency. Processing Latency State 1406 is introduced into the controller to maintain synchronization with the other components of the system. For example, the occurrence of any NUI or SFI during this state is an indication of loss of synchronization which is signaled in the F1 flag.

FPGA Implementation Example

Component 108 was implemented and validated for the Xilinx LX240T FPGA device employing the architecture proposed in this invention.

ZF equalization and linear interpolation methods were used.

The reference sequence generator used a CORDIC architecture to implement Zadoff-Chu.

The result of occupation of FPGA resources is presented in the following table: Table 1 - Use of FPGA Logic Resources

Claims (31)

1. Circuit architecture for channel estimation and distortion compensation in physical uplink channels of LTE and LTE-Advanced networks, characterized by the fact that it comprises a pipeline structure and multiple clock domain sections which include at least a first section, clocked Clk1, of spectral adjustment and SC-FDMA frame structure processing, a second section, clocked Clk2, of channel estimation, noise estimation and noise compensation and IQ unbalance, a third section, with clock Clk3, channel decoder and HARQ process management, with the exchange of messages and commands with the upper layers of the radio protocol stack performed by a fourth section, with clock Clk4. 2. Circuit architecture according to claim 1, characterized in that it comprises modules (106) specialized in the interface between said clock domain sections Clk1 and Clk2 through devices (110) associated with memory. 3. Circuit architecture according to claim 2, characterized in that the interface between said first and second clock domain sections comprises a module (106) associated with a ping-pong type memory (110). 4. Circuit architecture according to claim 3, characterized in that the assembly of the time-frequency frame associated with a subframe and subsequent provision of sequential data of each user for said second clock domain are executed by said interface module ( 106). 5. Circuit architecture according to claim 4, characterized in that said sequential data provision is performed by mapping physical channels and data flow according to the sequential data interface AXI Stream B. 6. Circuit architecture according to claim 5, characterized in that said first section comprises signaling (202), cyclic prefix removal (204), spectral adjustment (206) and FFT streaming (208) components . 7. Circuit architecture according to claim 6, characterized in that said signaling component (202) adds a control signaling for bursts of continuous data streams. 8. Circuit architecture according to claim 6, characterized in that said cyclic prefix removal component (204) marks as invalid, through control signaling, the signal samples corresponding to the cyclic prefix of the SC-FDMA signal. 9. Circuit architecture according to claim 6, characterized in that said spectral adjustment component (206) performs the temporal processing of the frequency deviation of the half subcarrier generated in the transmitter. 10. Circuit architecture according to claim 6, characterized in that said FFT streaming component (208) performs the FFT block transform processing. 11. Circuit architecture according to claim 1, characterized in that the degradations of the propagation medium are independently compensated for the physical channels PUSCH and PUCCH through the respective components Compens PUSCH (108) and Compens PUCCH (112). 12. Circuit architecture according to claim 11, characterized in that said Degradation Compensation component (108) is segmented into processing modules, through the Process (602) and IDFT (608) components, and the Estimation of Degradations (604) and Reference Signal Generation (606). 13. Circuit architecture according to claim 12, characterized in that said Process component (602) has a specific Control module (902) that is responsible for interpreting the control signaling of the input signal and for generating the signaling of output signal control, both signals conform to AXI Stream B interface. 14. Circuit architecture according to claim 13, characterized in that said Control component (902) operates in accordance with the State Machine A, and is also responsible for activating the processing of modules (904), (906) and (908) through the interpretation of specific signaling of the EstCh module (604), called ChEstDone. 15. Circuit architecture according to claim 13, characterized in that said Control component (902) is also responsible for the control interface dealings with Demapper (106), EstCh (604) and IDFT (606) modules to operate in accordance with Sequence A. 16. Circuit architecture according to claim 13, characterized in that said Process component (602) has a specific module (904) for Digital Processing of the signal from the Demapper (106) to compensate for degradations according to estimates made by the EstCh Module ( 106). 17. Circuit architecture according to claim 13, characterized in that said Processing component (602) has specific FIFO modules (906) and (908) to perform the alignment of the s_demap_tdata and s_chest_tdata signals, coming from the respective Demapper modules ( 106) and EstCh (604) to be processed by the Processing module (904). 18. Circuit architecture according to claim 12, characterized in that said IDFT component (608) receives blocks of consecutive valid signal samples, with specific lengths N, multiples of 12, signaled according to the AXI Stream A interface. computes the inverse fourier transform of the input signal and returns the transformed signal in the same AXI stream format as the input. The IDFT component (608) can signal busy to the processing module (602) only during intervals between signal sample blocks. 19. Circuit architecture according to claim 12, characterized in that said component EstCh (604) is responsible for providing estimates of degradations suffered for each sample of the s_demap_tdata signal that feeds the FIFO (908) for processing in (904) . 20. Circuit architecture according to claim 19, characterized in that said EstCh module (604) is segmented into specific circuits specialized in the processing of distortion estimates through the modules (1204) and (1208); in the control of processing and processing of signals through the module (1202); and in the data synchronization for the noise power estimation module NEst (1208). 21. Circuit architecture according to claim 20, characterized in that said control component (1202) is responsible for signaling dealings with the components Demapper (106), MemDMRS (408), GenRef (606) and Processing (602 ) in order to establish the execution process of Sequence Diagram B. 22. Circuit architecture according to claim 20, characterized in that said control component (1202) is responsible for interpreting the signaling of the s_ref_tdata reference signal that feeds the estimation module (1204); be responsible for generating the signaling of the m_chest_tdata output signal; and also be responsible for reading and writing control of the MemDMRS 408 memory to obtain the Data_from_Mem signal and write the Data_to_Mem signal with the estimated distortions. 23. Circuit architecture according to claim 20, characterized in that said control component (1202) implements and manages the State Machine B, which must dictate the behavior of the processing circuits (1204), (1206) and ( 1208). 24. Circuit architecture according to claim 20, characterized in that said ChEst Processing component (1204) is responsible for the estimation function of the degradations during the State Estimate Channel (1106) and for the interpolation of the estimates, either in time or frequency , to support equalization during the state (1110). 25. Circuit architecture according to claim 20, characterized in that said NESt Processing component (1208) performs an average estimate of the signal-to-noise power ratio per Resource Block (RB), during the State Estimate Channel (1106) . 26. Circuit architecture according to claim 20, characterized in that said component Alignment (1206) synchronizes the reference signal Data_from_Mem, coming from the memory (408), with the wk signal estimated by the module (1204). 27. Circuit architecture according to claim 12, characterized in that said component GenRef (606) is responsible for generating a reference signal (DMRS) for the component (604) according to the AXI Stream A interface. 28. Circuit architecture according to claim 27, characterized in that said component GenRef (606) is partitioned into a control (1502) and processing (1504) component. 29. Circuit architecture according to claim 28, characterized in that said Controller component (1502) is responsible for generating the control signaling of the AXI Stream interface for the reference signal 5 m_ref_tdata. 30. Circuit architecture according to claim 28, characterized in that said Controller component (1502) implements and manages the State Machine C, defining the operation of the processing component (1504) according to 10 Execution Sequence C. 31. Circuit architecture according to claim 28, characterized in that said Processing component (1504) is responsible for generating consecutive valid Zadoff-Chu reference signal samples for component EstCh (604) 15 during State GenerateRef (1404 ).

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