AU5697299A - Method and system for timing control in the testing of rambus memory modules - Google Patents

Method and system for timing control in the testing of rambus memory modules

Info

Publication number
AU5697299A
AU5697299A AU56972/99A AU5697299A AU5697299A AU 5697299 A AU5697299 A AU 5697299A AU 56972/99 A AU56972/99 A AU 56972/99A AU 5697299 A AU5697299 A AU 5697299A AU 5697299 A AU5697299 A AU 5697299A
Authority
AU
Australia
Prior art keywords
testing
timing control
memory modules
rambus memory
rambus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU56972/99A
Inventor
Paul R. Hunter
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tanisys Tech Inc
Original Assignee
Tanisys Tech Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/267,731 external-priority patent/US6285962B1/en
Application filed by Tanisys Tech Inc filed Critical Tanisys Tech Inc
Publication of AU5697299A publication Critical patent/AU5697299A/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
    • G01R31/31905—Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
    • G01R31/31908—Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns
    • G01R31/3191—Calibration
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/3193—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response
    • G01R31/31937—Timing aspects, e.g. measuring propagation delay
AU56972/99A 1998-08-26 1999-08-25 Method and system for timing control in the testing of rambus memory modules Abandoned AU5697299A (en)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US9789498P 1998-08-26 1998-08-26
US60097894 1998-08-26
US09267731 1999-03-15
US09/267,731 US6285962B1 (en) 1998-08-26 1999-03-15 Method and system for testing rambus memory modules
US35917399A 1999-07-22 1999-07-22
US09359173 1999-07-22
PCT/US1999/019752 WO2000013186A1 (en) 1998-08-26 1999-08-25 Method and system for timing control in the testing of rambus memory modules

Publications (1)

Publication Number Publication Date
AU5697299A true AU5697299A (en) 2000-03-21

Family

ID=27378466

Family Applications (1)

Application Number Title Priority Date Filing Date
AU56972/99A Abandoned AU5697299A (en) 1998-08-26 1999-08-25 Method and system for timing control in the testing of rambus memory modules

Country Status (2)

Country Link
AU (1) AU5697299A (en)
WO (1) WO2000013186A1 (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6801869B2 (en) 2000-02-22 2004-10-05 Mccord Don Method and system for wafer and device-level testing of an integrated circuit
AU6964401A (en) * 2000-06-06 2001-12-17 Igor Anatolievich Abrosimov Data processing system
DE10035169A1 (en) * 2000-07-19 2002-02-07 Infineon Technologies Ag Method and device for testing the setup time and hold time of signals of a circuit with clocked data transmission
AU2001296891A1 (en) * 2000-09-22 2002-04-02 Don Mccord Method and system for wafer and device-level testing of an integrated circuit
US6857089B2 (en) * 2001-05-09 2005-02-15 Teradyne, Inc. Differential receiver architecture
DE10125911A1 (en) * 2001-05-28 2002-12-12 Infineon Technologies Ag Testing of proprietary or manufacturer memory modules with a device that allows such modules to be tested with a standard system board, thus considerably lowering testing costs
DE102004020867A1 (en) * 2004-04-28 2005-11-24 Infineon Technologies Ag Semiconductor device test method, and data latch component
DE102004020866A1 (en) * 2004-04-28 2005-11-24 Infineon Technologies Ag Semiconductor device test method for testing memory module, by using clock signals shifted forward and back by predetermined period compared to normal operation
US7683630B2 (en) * 2006-11-30 2010-03-23 Electro Scientific Industries, Inc. Self test, monitoring, and diagnostics in grouped circuitry modules

Also Published As

Publication number Publication date
WO2000013186A1 (en) 2000-03-09

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase