AU3286399A - Circuit and method of cryptographic multiplication - Google Patents

Circuit and method of cryptographic multiplication

Info

Publication number
AU3286399A
AU3286399A AU32863/99A AU3286399A AU3286399A AU 3286399 A AU3286399 A AU 3286399A AU 32863/99 A AU32863/99 A AU 32863/99A AU 3286399 A AU3286399 A AU 3286399A AU 3286399 A AU3286399 A AU 3286399A
Authority
AU
Australia
Prior art keywords
circuit
cryptographic multiplication
cryptographic
multiplication
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU32863/99A
Inventor
Rashid A. Chaudhary
Philipp Michael Glaser
Michael J. Torla
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of AU3286399A publication Critical patent/AU3286399A/en
Abandoned legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/72Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
    • G06F7/728Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic using Montgomery reduction
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/72Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
    • G06F7/724Finite field arithmetic

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
AU32863/99A 1998-12-18 1999-02-05 Circuit and method of cryptographic multiplication Abandoned AU3286399A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US21593498A 1998-12-18 1998-12-18
US09215934 1998-12-18
PCT/US1999/002451 WO2000038047A1 (en) 1998-12-18 1999-02-05 Circuit and method of cryptographic multiplication

Publications (1)

Publication Number Publication Date
AU3286399A true AU3286399A (en) 2000-07-12

Family

ID=22804995

Family Applications (1)

Application Number Title Priority Date Filing Date
AU32863/99A Abandoned AU3286399A (en) 1998-12-18 1999-02-05 Circuit and method of cryptographic multiplication

Country Status (3)

Country Link
AU (1) AU3286399A (en)
TW (1) TW448376B (en)
WO (1) WO2000038047A1 (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10107376A1 (en) 2001-02-16 2002-08-29 Infineon Technologies Ag Method and device for modular multiplication and arithmetic unit for modular multiplication
US7711763B2 (en) * 2001-02-21 2010-05-04 Mips Technologies, Inc. Microprocessor instructions for performing polynomial arithmetic operations
WO2003052584A2 (en) * 2001-12-14 2003-06-26 Koninklijke Philips Electronics N.V. Pipelined core in montgomery multiplier
US20040252829A1 (en) * 2003-04-25 2004-12-16 Hee-Kwan Son Montgomery modular multiplier and method thereof using carry save addition
US7769797B2 (en) 2004-01-20 2010-08-03 Samsung Electronics Co., Ltd. Apparatus and method of multiplication using a plurality of identical partial multiplication modules
US8619977B2 (en) * 2008-01-15 2013-12-31 Inside Secure Representation change of a point on an elliptic curve
CN104503730A (en) * 2014-10-24 2015-04-08 山东华芯半导体有限公司 Instruction-based large-number point addition and point multiplication operation circuit and realization method
CN106961282A (en) * 2017-03-31 2017-07-18 山东超越数控电子有限公司 A kind of Hardware Implementation of the High Speed I BM algorithm structures based on binary BCH code
CN113031911A (en) * 2019-12-24 2021-06-25 上海寒武纪信息科技有限公司 Multiplier, data processing method, device and chip

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19644688B4 (en) * 1996-10-28 2005-06-16 Systemonic Ag Circuit arrangement of a digital multiplier module for processing binary numbers and elements made of GF (2m)
GB9707861D0 (en) * 1997-04-18 1997-06-04 Certicom Corp Arithmetic processor

Also Published As

Publication number Publication date
TW448376B (en) 2001-08-01
WO2000038047A1 (en) 2000-06-29

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase