AU2745102A - Method and apparatus for reducing branch latency - Google Patents

Method and apparatus for reducing branch latency

Info

Publication number
AU2745102A
AU2745102A AU2745102A AU2745102A AU2745102A AU 2745102 A AU2745102 A AU 2745102A AU 2745102 A AU2745102 A AU 2745102A AU 2745102 A AU2745102 A AU 2745102A AU 2745102 A AU2745102 A AU 2745102A
Authority
AU
Australia
Prior art keywords
apparatus
method
branch latency
reducing branch
reducing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
AU2745102A
Inventor
John L Redford
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ChipWrights Design Inc
Original Assignee
ChipWrights Design Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US71069900A priority Critical
Application filed by ChipWrights Design Inc filed Critical ChipWrights Design Inc
Priority to PCT/US2001/049653 priority patent/WO2002039272A1/en
Publication of AU2745102A publication Critical patent/AU2745102A/en
Application status is Pending legal-status Critical

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802Instruction prefetching
    • G06F9/3804Instruction prefetching for branches, e.g. hedging, branch folding
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling, out of order instruction execution
    • G06F9/3842Speculative instruction execution
    • G06F9/3846Speculative instruction execution using static prediction, e.g. branch taken strategy
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44Arrangements for executing specific programs
    • G06F9/448Execution paradigms, e.g. implementations of programming paradigms
    • G06F9/4482Procedural
    • G06F9/4484Executing subprograms
    • G06F9/4486Formation of subprogram jump address
AU2745102A 2000-11-10 2001-11-09 Method and apparatus for reducing branch latency Pending AU2745102A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US71069900A true 2000-11-10 2000-11-10
PCT/US2001/049653 WO2002039272A1 (en) 2000-11-10 2001-11-09 Method and apparatus for reducing branch latency

Publications (1)

Publication Number Publication Date
AU2745102A true AU2745102A (en) 2002-05-21

Family

ID=24855140

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2745102A Pending AU2745102A (en) 2000-11-10 2001-11-09 Method and apparatus for reducing branch latency

Country Status (3)

Country Link
AU (1) AU2745102A (en)
TW (1) TW559733B (en)
WO (1) WO2002039272A1 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7493607B2 (en) 2002-07-09 2009-02-17 Bluerisc Inc. Statically speculative compilation and execution
US20050114850A1 (en) 2003-10-29 2005-05-26 Saurabh Chheda Energy-focused re-compilation of executables and hardware mechanisms based on compiler-architecture interaction and compiler-inserted control
US7996671B2 (en) 2003-11-17 2011-08-09 Bluerisc Inc. Security of program executables and microprocessors based on compiler-architecture interaction
US8607209B2 (en) 2004-02-04 2013-12-10 Bluerisc Inc. Energy-focused compiler-assisted branch prediction
US20080126766A1 (en) 2006-11-03 2008-05-29 Saurabh Chheda Securing microprocessors against information leakage and physical tampering

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3940450A1 (en) * 1989-12-07 1991-06-13 Voith Gmbh J M doctor device
CA2045790A1 (en) * 1990-06-29 1991-12-30 Richard Lee Sites Branch prediction in high-performance processor
EP0671685B1 (en) * 1994-03-08 1998-11-04 Digital Equipment Corporation Method and apparatus for detecting and executing cross-domain calls in a computer system
US5608886A (en) * 1994-08-31 1997-03-04 Exponential Technology, Inc. Block-based branch prediction using a target finder array storing target sub-addresses

Also Published As

Publication number Publication date
TW559733B (en) 2003-11-01
WO2002039272A9 (en) 2003-09-04
WO2002039272A1 (en) 2002-05-16

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