AU2020101601A4 - Circuit Implementation of a Multi-memristive and Multi-wing Chaotic System - Google Patents
Circuit Implementation of a Multi-memristive and Multi-wing Chaotic System Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/001—Modulated-carrier systems using chaotic signals
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0002—Multistate logic
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/84—Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/001—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols using chaotic signals
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
- H04L2209/12—Details relating to cryptographic hardware or logic circuitry
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Abstract
This invention discloses a multi-memristive and multi-wing chaotic system circuit that is
composed of four channel circuits: the first channel circuit is consisted of an inverter U1A, an
inverted integrator U2A and inverter U3A, a multiplier Al and a resistor. The second channel
circuit is composed of an inverter UlB, an inverting integrator U2B and an amplifier U3B, a
multiplier A2, and a resistor. The third channel circuit is composed of the inverter U1C, the
inverting integral integrator U2C and an oscillator U3C, the multiplier A3 and the resistor.
The fourth channel circuit is composed of an inverter UlD, an inverted integrator U2D,
multipliers A4 and A5, an addition circuit, and a resistor. In this invention, the memristive
chaotic system is extend to a plurality of memristors that acts on the chaotic circuit, which is
able to generate multi-wing chaotic attractors, and the dynamic behaviour of the system is
more complex. The invention provides a novel method for applying a memristor to a multi
wing chaotic circuit, and the generated chaotic signal is used in the fields of communication
security, information encryption and the alike.
-1/15
R1 R21 C1 R4
A1 x -'M A
21.7kn 10 10nF 10kn
: 13 11 - 16 R20 U2A 3
1kn 10kW 20R5 -,2 U3A
0.1 1Memristive 0 x+0k
circuitA 100kn 0 + -x
A2 R5 R19 C2 R
z -y -v vr
x X ~2 r_U110F0k
0.1 V/V 0 V 1kQ 1R8 e U2B 7
cicit B y 10 1
-Z _ s c3- R14
A3 20k.0 10kn
2 U1C2 R16 10nF 10I
0.1 V/V 0 V 1knQ 3 U3CR
Memristive 0 z 10k
circuit C 100knl +F -z
R23 C4
10kQ R26
R22 UID 10nF kI
R2 7 1 IC=0.1V A4 AS50k y R24 U2D1
10kI - 90 x 61 R25 63 U3
--0.1 V/V 0 V 0.1 V/V 0 V 33.3k (A, B,C)
(y,-z,-x) 4 5T
Figure 1
Description
-1/15
R1 R21 C1 R4 A1 x -'M A 21.7kn 10 10nF 10kn : 13 11 - 16 R20 U2A 3 1kn 10kW 20R5 -,2 U3A 0.1 1Memristive 0 x+0k circuitA 100kn 0 + -x
A2 R5 R19 C2 R z -y -v vr
x X ~2 r_U110F0k 0.1 V/V 0 V 1kQ 1R8 e U2B 7
cicit B y 10 1
-Z _ s c3- R14 A3 20k.0 10kn
2 U1C2 R16 10nF 10I
1knQ 3 U3CR 0.1 V/V 0 V Memristive 0 z 10k circuit C 100knl +F -z
R23 C4 10kQ R26 R22 UID 10nF kI R2 7 1 IC=0.1V A4 AS50k y R24 U2D1 10kI - 90 x 61 R25 63 U3
-- 0.1 V/V 0 V 0.1 V/V 0 V 33.3k (A, B,C) (y,-z,-x) 4 5T
Figure 1
PATENTS ACT 1990
Circuit Implementation of a Multi-memristive and Multi-wing Chaotic System
The invention is described in the following statement:-
The invention relates to a multi-memristive and multi-wing chaotic system circuit, and
belongs to the technical field of memristic chaotic system design
As the fourth basic component of the circuit, the memristor has been proposed by Cai
Shaotang since 1971, and realized by the HP laboratory in 2008 by using nano technology,
which has been widely studied and applied in various fields. Especially, the application of
memristor in chaotic circuit has caused the upsurge of domestic and international scholars'
research.
In recent year, that design of memristive chaotic circuits is a hot topic, and the study of
multi-memristic and multi-wing chaotic system is still relatively few, and the dynamic
behaviour of this system is more complex. The generated chaotic signal can be used in
communication security and information encryption, and the design method of this kind
of multi-memristive chaotic system can also be applied to other chaotic systems, which
has a broad application prospect.
An object of the present invention is to provide a method for designing a circuit of a multi
memristor and multi-wing chaotic system, wherein the output signal of the system has
stronger chaotic characteristics, and enhancing the complexity of a key space.
The technical scheme adopted by the present invention is as below
1. Implementation of a multi-memristive and multi-wing chaotic system whose
characteristic is that the circuit is composed of four channels: The first channel circuit
consists of an summator U1A, an inverted integrator U2A and an inverter U3A, a multiplier
Al and resistors RI, R2, R3, R4 and R15, Resistor R20, and resistor R21, the second
channel circuit consisting of inverter UlB, inverted integrator U2B and inverter U3B,
multiplier A2 and resistor R5, resistor R6, resistor R7, resistor R8, resistor R9, resistor RI8
and resistor 19. The third channel circuit consists of an inverter U1C, an inverted integrator
U2C, and an inverter U3C multiplier A3, and resistors RI0, RI1, R12, R13, R14, R16, and
R17. The fourth channel circuit consists of an inverter UlD, an inverted integrator U2D, a
multiplier A4, an addition circuit, and resistors R22, R23, and R24.
The output signal of the first-channel inverting integrator U2A is applied to the first channel
circuit via the resistor RI, and the signal is further applied to a second channel via the
multiplier A2, and to a third channel via a multiplier A3. The output signal is also applied
to the fourth channel via an inverter U3A connected to an summator circuit, and the output
signal of the second-channel inverted integrator U2B is applied to a first channel connected
to a multiplier A,connecting multiplier A3 applied to the third channel, connecting resistor
R22 and connecting the summator circuit applied on the forth channel, the output
signal is also applied to the second channel via an inverter U3B in connection with resistor
R5; the output of the third channel inverted integrator U2C is applied to a second channel
in connection with the multiplier A2, the output signal is applied on the first channel
connected to Multiplier Al through the inverter U3C, the connection resistor R10 is applied
on the second channel, connecting the summator circuit applies on the forth channel, the
information output by the fourth channel(A,B,C), A is in connection with resistor R3
applying on the first channel, B is in connection with resistor R7 applying on a second
channel, and C is in connection with resistor R12 applying upon the third channel.
According to claim 1, the multi-memristive and multi-wing chaotic system circuit is
characterized in adding operation circuit that comprises three modules, The first module is
composed of multiplier A5, operational amplifier U3D and resistor, the second module is
composed of multiplier A6, operation amplifier U4D and resistor and the third module is
composed of multiplier A7, operating amplifier U5D and resistor.
According to claim 1, the multi-memristive and multi-wing chaotic system circuit is
characterized in addition circuit can be designed to comprise one module, two modules and
three modules.
FIG. 1 is a schematic circuit diagram of the present invention;
FIG. 2 is a circuit diagram of a mono-memristive multi-wing chaotic system 1;
FIG. 3 is a circuit diagram of a mono-memristive multi-wing chaotic system 2;
FIG. 4 is a circuit diagram of a mono-memristive multi-wing chaotic system 3;
FIG. 5 is a circuit diagram of the double memorials block multi-wing chaotic system 1;
FIG. 6 is a circuit diagram of the double memorials block multi-wing chaotic system 2;
FIG. 7 is a circuit diagram of the double memristor multi-wing chaotic system 3;
FIG. 8 is a circuit diagram of a tri-memristive multi-wing chaotic system;
FIG. 9 is a plan view of the Y-Z phase of the circuit of the mono-memristive multi-wing chaotic system 1;
FIG. 10 is a plan view of the Y-Z phase of the circuit of the mono-memristive multi-wing chaotic system 2;
FIG. 11 is a plan view of the Y-Z phase of the circuit of the mono-memristive multi-wing chaotic system 3;
FIG. 12 is a plan view of the Y-Z phase of the circuit of the two-memristor multi-wing chaotic system 1;
FIG. 13 is a plan view of the Y-Z phase of the circuit of the two-memristor multi-wing chaotic system 2;
FIG. 14 is a plan view of the Y-Z phase of the circuit of the two-memristor multi-wing chaotic system 3;
FIG. 15 is a Y-Z phase plan of a tri-memristive multi-wing chaotic system circuit.
Hereinafter, that present invention will be further describe in detail with reference to the accompanying drawing and their detailed description
The memristor model of the present invention is as follows:
dq(#) d(a#+8 3) -3 2 w(#5)= a+3p#___ d# d#
q(o) is Magnetron memristive, 0 is magnetic flux, a, p is a parameter greater than
zero
The mathematical model involved in the present invention is as follows:
i = ax - yz+kw(u)y pY=-by +xz- z z=-x -cz +xy a= 4.6, b=12,c = 5,k =1
In above model, x, y, z, and u are state variables.
According to the present invention, the simulation circuit is composed of a first, a second, a third channel and a fourth channel, the first, the second and the third channel respectively implementing first, second and third functions in the above mathematical model, The fourth channel implements the fourth function and the memristive function w(u)
As shown in fig. 1, the multi-memristive and multi-wing chaotic system circuit of the
present invention, in the first channel circuit, the output of the invert integrator U2A is
signal X, in the second channel circuit, the output of inverted integrator U2B is signal Y , and in the third channel circuit, the output of inverted integrator U2C is signal Z . In the fourth channel, the addition circuit outputs three signals (A, B, C). In the circuit, the resistors and capacitors are standard components, the amplifiers are LF347BN, and the multipliers are AD633.
As shown in FIG. 2, the circuit of the mono-memristive and multi-wing chaotic system 1
is composed of first, second, third and fourth channel circuits, The first channel circuit is
composed of an summator U1A, an inverse integrator U2A, an inverter U3A, and
resistors RI, R2, R3, R4, a resistor R15, a resistance R20, and a resistor 21. The second
channel circuit is composed of an inverter UlB, an inverting integrator U2B, and inverter
U3B, a memristive circuit B, a multiplier A2, and resistors R5, R6, R7, R8, R9, R18, and
R19. The third channel circuit is composed of an inverter U1C, an inverted integrator
U2C, and an inverter U3C, a memristive circuit C, a multiplier A3, and a resistor R10, a
resistor RI1, resistor R12, resistor R13, resistance R14, resistor B16, and resistor R17.
The fourth channel circuit is composed of an inverter UlD, an inverted integrator U2D,
multipliers A4 and A5, an operational amplifier U3D, and resistors R22, R23, R24, R25,
R26, and R27; The output signal of the first-channel inverting integrator U2A is
connected with the resistor RI to apply on thefirst channel circuit,
And the output signal is further applied to a second channel via connecting the multiplier
A2, and connecting the multiplier A3 to apply on the third channel, and connecting the
output signal of the second-channel inverting integrator U2B to the multiplier Al to apply
on the first channel and connecting multiplier A3 to apply on the third channel,
connecting resistor R22 is connected to the multiplier A5, a connection resistor R27 acting on the fourth channel, the output signal is also applied to the second channel via the connection resistor R5 of inverter U3B; the output of the third channel inverted integrator U2C is applied to a second channel in connection with the multiplier A2, The output signal via the inverter U3C connecting the multiplier Al applies on the first channel , connecting the connection resistor RI to apply on the third channel. The output connection resistor R3 of the fourth channel inverter U3D is applied to the first channel.
As shown in FIG. 3, the circuit of the mono-memristive and multi-wing chaotic system 2
is composed of the first, second, third and fourth channel circuits. The first channel
circuit is composed of an summator U1A, an inverse integrator U2A, an inverter U3A,
and resistors RI, R2, R3, R4, a resistor R15, a resistance R20, and a resistor 21. The
second channel circuit is composed of an inverter UIB, an inverting integrator U2B, and
inverter U3B, a memristive circuit B, a multiplier A2, and resistors R5, R6, R7, R8, R9,
R18, and R19. The third channel circuit is composed of an inverter UIC, an inverted
integrator U2C, and an inverter U3C, a memristive circuit C, a multiplier A3, and a
resistor RIO, a resistor RI1, resistor R12, resistor R13, resistance R14, resistor B16, and
resistor R17. The fourth channel circuit is composed of an inverter UlD, an inverted
integrator U2D, multipliers A4 and A5, an operational amplifier U3D, and resistors R22,
R23, R24, R25, R26, and R27; The output signal of thefirst-channel inverting integrator
U2A is applied to the first channel circuit via connecting the resistor RI, and is further
applied to a second channel via the multiplier A2. Connecting the multiplier A3 to apply
on the third channel, connecting resistor R22 to apply on the fourth channel,the output signal is also applied to the second channel via an inverter U3B connecting the resistor
R5 and the output of the third channel inverted integrator U2C is applied on a second
channel in connection with the multiplier A2, the output signal applies on the first
channel through the inverter U3C,and connecting the multiplier Al, and connecting
resistor RI to apply on the third channel, and connecting the multiplier A5, and resistor
R27 to apply on the fourth channel. The output of operational amplifier U3D connects to
resistor R7 to apply on the second channel.
As shown in Fig 4: The circuit of the single memristor multi-wing chaotic system 3 is
composed of the first, second, third and fourth channel circuits. The first channel circuit
consists of an addition operation U1A, an inverter integrator U2A, an inverter U3A, and
resistors RI, R2, R3, R4, R15, R20, and R21. The second channel circuit consists of an
inverter UIB, an inverter integrator U2B, an inverter U3B, a memristor circuit B, a
multiplier A2, and resistors R5, R6, R7, R8, R9, R18, and R19. The third channel circuit
consists of an inverter UIC, an inverter integrator U2C, an inverter U3C, a memristor
circuit C, a multiplier A3, and a resistor RIO, a resistor RI1, a resistor R12, a resistor
R13, a resistor R14, a resistor R16, and a resistor R17. The fourth channel circuit consists
of an inverter UlD, an inverter integrator U2D, multipliers A4 and A5, an addition
operation U3D, and a resistor R22, a resistor R23, a resistor R24, a resistor R25, a resistor
R26 and a resistor R27; The output signal of the first channel inverter integrator U2A is
connected with the resistor RI to act on the first channel circuit, the output signal is also
connected with the multiplier A2 to act on the second channel, the connection multiplier
A3 to act on the third channel, the output signal is also connected with the multiplier A5 through the inverter, and the resistor R27 acts on the fourth channel; The output signal of the second channel inverter integrator U2B is connected to the multiplier Al to act on the first channel, the connection multiplier A3 to act on the third channel, and the connection resistor R22 to act on the fourth channel. The output signal is also connected to the second channel through the connection resistor R5 of the inverter U3B. The output signal of the third channel inverter integrator U2C is connected to the multiplier A2 to act on the second channel, the output signal is connected to the multiplier Al to act on the first channel through the inverter U3C, and the connection resistor RI acts on the third channel. The output connection resistor R12 of the fourth channel inverter U3D acts on the third channel.
As shown in Figure 5: The circuit of the double memristor multi-wing chaotic system 1,
Consisting of first, second, third and fourth channels, The first channel circuit consists of
an addition operation UlA, an inverter integrator U2A, an inverter U3A, and resistors RI,
R2, R3, R4, RI5, R20, and R21, The second channel circuit consists of an inverter UIB,
an inverter integrator U2B, an inverter U3B, a multiplier A2, and resistors R5, R6, R7,
R8, R9, R18, and R19. The third channel circuit consists of an inverter UiC, an inverter
integrator U2C, an inverter U3C, a multiplier A3, and a resistor RIO, a resistor RI1, a
resistor R12, a resistor R13, a resistor R14, a resistor R16, and a resistor R17. The fourth
channel circuit consists of an inverter UlD, an inverter integrator U2D, multipliers A4
and A5, an operational amplifier U3D, an operational amplifier U4D, and a resistor R22,
a resistor R23, a resistor R24, a resistor R25, a resistor R26, a resistor R27, a resistor
R28, a resistor R29 and a resistor R30; The output signal of the first channel inverter integrator U2A is connected to the resistor RI to act on the first channel circuit, the output signal is also connected to the multiplier A2 to act on the second channel, and the connection multiplier A3 to act on the third channel; The output signal of the second channel inverter integrator U2B is connected to the multiplier Al to act on the first channel, the connection multiplier A3 to act on the third channel, the connection resistor
R22, the connection multiplier A5 and the connection resistor R27 to act on the fourth
channel, and the output signal is also connected to the second channel through the
connection resistor R5 of the inverter U3B; The output signal of the third channel inverter
integrator U2C is connected to the multiplier A2 to act on the second channel, the output
signal is connected to the multiplier Al to act on thefirst channel through the inverter
U3C, the connection resistor RI to act on the third channel, the connection resistor
multiplier A6, and the connection resistor R28 to act on the fourth channel; The output
connection resistance R3 of the fourth channel operational amplifier U3D acts on the first
channel, and the output connection resistance R7 of the operational amplifier U4D acts
on the second channel.
As shown in Figure 5: The circuit of the double memristor multi-wing chaotic system 1
consists of the first, second, third and fourth channels. The first channel circuit consists of
an addition operation UlA, an inverter integrator U2A, an inverter U3A, and resistors RI,
R2, R3, R4, RI5, R20, and R21, The second channel circuit consists of an inverter UIB,
an inverter integrator U2B, an inverter U3B, a multiplier A2, and resistors R5, R6, R7,
R8, R9, R18, and R19. The third channel circuit consists of an inverter UiC, an inverter
integrator U2C, an inverter U3C, a multiplier A3, and a resistor RIO, a resistor RI1, a resistor R12, a resistor R13, a resistor R14, a resistor R16, and a resistor R17. The fourth channel circuit consists of an inverter UlD, an inverter integrator U2D, multipliers A4 and A5, an operational amplifier U3D, an operational amplifier U4D, and a resistor R22, a resistor R23, a resistor R24, a resistor R25, a resistor R26, a resistor R27, a resistor
R28, a resistor R29 and a resistor R30; The output signal of thefirst channel inverter
integrator U2A is connected to the resistor RI to act on the first channel circuit, the
output signal is also connected to the multiplier A2 to act on the second channel, and the
connection multiplier A3 to act on the third channel; The output signal of the second
channel inverter integrator U2B is connected to the multiplier Al to act on the first
channel, the connection multiplier A3 to act on the third channel, the connection resistor
R22, the connection multiplier A5 and the connection resistor R27 to act on the fourth
channel, and the output signal is also connected to the second channel through the
connection resistor R5 of the inverter U3B; The output signal of the third channel inverter
integrator U2C is connected to the multiplier A2 to act on the second channel, the output
signal is connected to the multiplier Al to act on thefirst channel through the inverter
U3C, the connection resistor RI to act on the third channel, the connection resistor
multiplier A6, and the connection resistor R28 to act on the fourth channel; The output
connection resistance R3 of the fourth channel operational amplifier U3D acts on the first
channel, and the output connection resistance R7 of the operational amplifier U4D acts
on the second channel.
As shown in Figure 6: The circuit of the double memristor multi-wing chaotic system 2,
Consisting of the first, second, third and fourth channels. The first channel circuit consists of an addition operation U1A, an inverter integrator U2A, an inverter U3A, and resistors
R1, R2, R3, R4, R15, R20, and R21. The second channel circuit consists of an inverter
UlB, an inverter integrator U2B, an inverter U3B, a multiplier A2, and resistors R5, R6,
R7, R8, R9, R18, and R19. The third channel circuit consists of an inverter U1C, an
inverter integrator U2C, an inverter U3C, a multiplier A3, and a resistor R10, a resistor
RI1, a resistor R12, a resistor R13, a resistor R14, a resistor R16, and a resistor R17. The
fourth channel circuit consists of an inverter UlD, an inverter integrator U2D, multipliers
A4 and A5, an operational amplifier U3D, an operational amplifier U4D, and a resistor
R22, a resistor R23, a resistor R24, a resistor R25, a resistor R26, a resistor R27, a
resistor R28, a resistor R29 and a resistor R30; The output signal of the first channel
inverter integrator U2A is connected with the resistor RI to act on thefirst channel
circuit, the connection multiplier A2 to act on the second channel, connecting multiplier
A3 to act on the third channel, the output signal is also connected with the multiplier A6
through the inverter U3A, and connection resistor R28 acts on the fourth channel; The
output signal of the second channel inverter integrator U2B is connected to the multiplier
Al to act on thefirst channel, and connecting multiplier A3 to act on the third channel,
connecting resistor R22, and multiplier A5 and resistor R27 to act on the fourth channel,
and the output signal is also connected to the second channel through the connection
resistor R5 of the inverter U3B; The output signal of the third channel inverter integrator
U2C is connected to the multiplier A2 to act on the second channel, the output signal is
connected to the multiplier Al to act on thefirst channel through the inverter U3C, and
connecting resistor R10 acts on the third channel; The output connects resistance R3 of the fourth channel operational amplifier U3D to act on the first channel, and the output connects resistance R12 of the operational amplifier U4D to act on the third channel.
As shown in Figure 7: The circuit of the double memristor and multi-wing chaotic system
3, Consisting of the first, second, third and fourth channels. The first channel circuit
consists of an addition operation U1A, an inverter integrator U2A, an inverter U3A, and
resistors RI, R2, R3, R4, R15, R20, and R21, The second channel circuit consists of an
inverter UlB, an inverter integrator U2B and an inverter U3B, a multiplier A2, and
resistors R5, R6, R7, R8, R9, R18 and R19. The third channel circuit consists of inverter
U1C, inverter integrator U2C, inverter U3C, multiplier A3, resistor RIO, resistor RI1,
resistor R12, resistor R13, resistor R14, resistor R16 and resistor R17. The fourth channel
circuit consists of inverter UlD, inverter integrator U2D, multiplier A4 and A5,
operational amplifier U3D, operational amplifier U4D, resistor R22, resistor R23, resistor
R24, resistor R25, resistor R26, resistor R27, resistor R28, resistor R29 and resistor R30;
The output signal of the first channel inverter integrator U2A is connected with the
resistor RI to act on the first channel circuit, connecting multiplier A2 to act on the
second channel, and connecting multiplier A3 to act on the third channel. The output
signal is also connected with the multiplier A6 through the connection resistor of the
inverter U3A, and connecting resistor R28 acts on the fourth channel. The output signal
of the second channel inverter integrator U2B is connected to the multiplier Al to act on
the first channel, connecting multiplier A3 to act on the third channel, and connecting
resistor R22 to act on the fourth channel. The output signal is also connected to the
second channel through the connection resistor R5 of the inverter U3B. The output signal of the third channel inverter integrator U2C is connected to the multiplier A2 to act on the second channel, the output signal is connected to the multiplier Al to act on the first channel through the inverter U3C, connecting resistor RI to act on the third channel, connecting multiplier A5 and resistor R27 to act on the fourth channel; The output connecting resistor R7 of the fourth channel operational amplifier U3D to act on the second channel, and the output connection resistor R12 of the operational amplifier U4D acts on the third channel.
As shown in FIG. 8: The three memristors multi-wing chaotic system circuit, Consisting
of first, second, third and fourth channels. The first channel circuit consists of an addition
operation U1A, an inverter integrator U2A, an inverter U3A, and resistors RI, R2, R3,
R4, R15, R20, and R21. The second channel circuit consists of an inverter UIB, an
inverter integrator U2B and an inverter U3B, a multiplier A2, and resistors R5, R6, R7,
R8, R9, R18 and R19.The third channel circuit consists of an inverter UiC, an inverter
integrator U2C and an inverter U3C, a multiplier A3, and resistors RIO, RI1, R12, R13,
R14, R16 and R17. The fourth channel circuit consists of an inverter UlD, an inverter
integrator U2D, multipliers A4, A5, A6 and A7, an operational amplifier U3D, an
operational amplifier U4D, an operational amplifier U5D, and resistors R22, R23, R24,
R25, R26, R27, R28, R29, R30, R31, R32 and R33; The output signal of thefirst channel
inverter integrator U2A is connected with the resistor RI to act on thefirst channel
circuit, connecting multiplier A2 to act on the second channel, connecting multiplier A3
to act on the third channel, the output signal is also connected with the multiplier A7
through the inverter U3A, and connecting resistor R32 to act on the fourth channel; The
output signal of the second channel inverter integrator U2B is connected to the multiplier
Al to act on the first channel, and connecting multiplier A3 to act on the third channel,
connecting resistor R22 and multiplier A5 and resistor R27 to act on the fourth channel,
and the output signal is also connected to the second channel through the connection
resistor R5 of the inverter U3B; The output signal of the third channel inverter integrator
U2C is connected to the multiplier A2 to act on the second channel, the output signal is
connected to the multiplier Al to act on the first channel through the inverter U3C,
connecting R10 to act on the third channel, and connecting multiplier A6 and resistor R28
to act on the fourth channel; The output connecting resistance R3 of the fourth channel
operational amplifier U3D to act on the first channel, the output connecting resistance R7
of the operational amplifier U4D to act on the second channel, and the output connecting
resistance R12 of the operational amplifier U5D to act on the third channel.
Claims (4)
1. An Implementation of a multi-memristive and multi-wing chaotic system whose
characteristic is that the circuit is composed of four channels: The first channel circuit
consists of an summator U1A, an inverted integrator U2A and an inverter U3A, a multiplier
Al and resistors RI, R2, R3, R4 and R15, Resistor R20, and resistor R21, the second
channel circuit consisting of inverter UlB, inverted integrator U2B and inverter U3B,
multiplier A2 and resistor R5, resistor R6, resistor R7, resistor R8, resistor R9, resistor RI8
and resistor 19. The third channel circuit consists of an inverter U1C, an inverted integrator
U2C, and an inverter U3C multiplier A3, and resistors RI0, RI1, R12, R13, R14, R16, and
R17. The fourth channel circuit consists of an inverter UlD, an inverted integrator U2D, a
multiplier A4, an addition circuit, and resistors R22, R23, and R24; and wherein the output
signal of the first-channel inverting integrator U2A is applied to the first channel circuit
via the resistor RI, and the signal is further applied to a second channel via the multiplier
A2, and to a third channel via a multiplier A3. The output signal is also applied to the fourth
channel via an inverter U3A connected to an summator circuit, and the output signal of the
second-channel inverted integrator U2Bis applied to a first channel connected to a
multiplier Al,connecting multiplier A3 applied to the third channel, connecting resistor
R22 and connecting the summator circuit applied on the forth channel, the output signal is
also applied to the second channel via an inverter U3B in connection with resistor R5; the
output of the third channel inverted integrator U2C is applied to a second channel in
connection with the multiplier A2, the output signal is applied on the first channel
connected to Multiplier A l through the inverter U3C, the connection resistor RI0 is applied
on the second channel, connecting the summator circuit applies on the forth channel, the information output by the fourth channel(A,B,C), A is in connection with resistor R3 applying on the first channel, B is in connection with resistor R7 applying on a second channel, and C is in connection with resistor R12 applying upon the third channel.
2. The system of claim 1, wherein the multi-memristive and multi-wing chaotic
system circuit is characterized in adding operation circuit that comprises three modules,
The first module is composed of multiplier A5, operational amplifier U3D and resistor, the
second module is composed of multiplier A6, operation amplifier U4D and resistor and the
third module is composed of multiplier A7, operating amplifier U5D and resistor.
3. The system of claim 1, wherein the multi-memristive and multi-wing chaotic
system circuit is characterized in addition circuit can be designed to comprise one module,
two modules and three modules.
4. The system of claim 1, wherein The multi-memristive and multi-wing chaotic
system circuit is characterized in that when the addition circuit mentioned comprises a
module, it is composed of a multiplier A5, an operational amplifier U3D, and resistors R25,
R26, and R27; when the addition circuit mentioned comprises two modules, it is composed
of multipliers A5 and A6, operational amplifiers U3D and U4D, and resistors R25, R26,
R27, R28, R29, and R30; when the mentioned addition circuit comprises three modules, it
is composed of multipliers A5, A6 and A7, operational amplifiers U3D, U4D and U5D,
and resistors R25, R26, R27, R28, R2, R30, R31, R32 and R30.
-1/15- 31 Jul 2020
R1 R21 C1 R4 A1 x y Y 21.7kΩ 10kΩ 10nF 10kΩ R2 U1A 13 11 U2A 3 -z X 16 R20 18 1kΩ U3A 10kΩ 20 R15 22 0.1 V/VMemristive 0V R3 忆阻电路A 0 0 x 10kΩ circuitA 100kΩ 0 -x 2020101601
A2 R5 R19 C2 z Y -y R9 6 8.3kΩ 10kΩ 10nF x X U1B 10kΩ R6 2 0.1 V/V 0 V 1kΩ U2B 7 10 R18 9 R7 U3B Memristive 忆阻电路B 0 10kΩ 15 R8 8 circuit B 100kΩ 0 y 10kΩ 0 -y
R10 5 R17 C3 -z R14 A3 20kΩ 10kΩ y Y 10nF 10kΩ U1C x X 21 R11 1 U2C 1kΩ 24 R16 23 R13 U3C 0.1 V/V 0 V 10kΩ 17 19 R12 0 z Memristive 0 10kΩ 忆阻电路C 0 -z circuit C 100kΩ
R23 C4 10kΩ R26 10nF R22 U1D 10kΩ 57 IC=0.1V A4 A5 y U2D 58 R24 12 Y Y 10kΩ 59 61 U3D 10kΩ 60 X X 62 R25 63 0 0 33.3kΩ 0.1 V/V 0 V 0.1 V/V 0 V (A,B,C) R27 0 (y,-z,-x) 4 50kΩ
Figure 1
-2/15- 31 Jul 2020
R1 R21 C1 R4 A1 x y Y 21.7kΩ 10kΩ 10nF 10kΩ R2 U1A 13 11 U2A 3 16 R20 X -z 18 1kΩ U3A 20 R15 22 2020101601
0.1 V/V 0 V 10kΩ R3 0 x 10kΩ A 0 100kΩ 0 -x
A2 R5 R19 C2 z Y -y R9 6 8.3kΩ 10kΩ 10nF x X U1B 10kΩ R6 2 0.1 V/V 0 V 1kΩ U2B 7 10 R18 9 R7 U3B 0 10kΩ 15 R8 8 -z 100kΩ y 10kΩ 0 0 -y
R10 5 R17 C3 -z R14 A3 20kΩ 10kΩ y Y 10nF 10kΩ U1C x X 21 R11 1 U2C 1kΩ 24 R16 23 R13 U3C 0.1 V/V 0 V 10kΩ 17 19 R12 0 z 0 10kΩ -x 100kΩ 0 -z
R23 C4 10kΩ 10nF R22 U1D R26 4 A4 y R24 U2D Y 10kΩ 3 5 10kΩ A5 10kΩ 2 X 1 Y 7 0 A U3D 0 R25 X 10 6 0.1 V/V 0 V y 33.3kΩ 0.1 V/V 0 V R27 0 A y 50kΩ
Figure 2
-3/15- 31 Jul 2020
R1 R21 C1 R4 A1 x y Y 21.7kΩ 10kΩ 10nF 10kΩ R2 U1A 13 11 U2A 3 16 R20 X -z 18 1kΩ U3A 10kΩ 20 R15 22 0.1 V/V 0 V R3 0 0 x 10kΩ y 100kΩ 0 -x 2020101601
R5 R19 C2 A2 -y R9 z Y 8.3kΩ 10kΩ 10nF U1B 10kΩ 6 R6 2 x X
1kΩ U2B 7 10 R18 9 0.1 V/V 0 V R7 U3B 0 10kΩ 15 R8 8 B 100kΩ y 10kΩ 0 0 -y
R10 5 R17 C3 -z R14 A3 20kΩ 10kΩ y Y 10nF 10kΩ U1C x X 21 R11 1 U2C 1kΩ 24 R16 23 R13 U3C 0.1 V/V 0 V 10kΩ 17 19 R12 0 z 0 10kΩ -x 100kΩ 0 -z
R23 C4 10kΩ 10nF R22 U1D R26 4 A4 y R24 U2D Y 10kΩ 3 5 10kΩ A5 10kΩ 2 X 1 Y 7 0 A U3D 0 R25 X 10 6 0.1 V/V 0 V y 33.3kΩ 0.1 V/V 0 V R27 0 B -z 50kΩ
Figure 3
-4/15- 31 Jul 2020
R1 R21 C1 R4 A1 x y Y 21.7kΩ 10kΩ 10nF 10kΩ R2 U1A 13 11 U2A 3 16 R20 X -z 18 1kΩ U3A 10kΩ 20 R15 22 0.1 V/V 0 V R3 0 0 x 10kΩ y 100kΩ 0 -x 2020101601
A2 R5 R19 C2 z Y -y R9 6 8.3kΩ 10kΩ 10nF x X U1B 10kΩ R6 2 0.1 V/V 0 V 1kΩ U2B 7 10 R18 9 R7 U3B 0 10kΩ 15 R8 8 -z 100kΩ y 10kΩ 0 0 -y
R10 5 R17 C3 -z R14 A3 20kΩ 10kΩ y Y 10nF 10kΩ U1C x X 21 R11 1 U2C 1kΩ 24 R16 23 R13 U3C 0.1 V/V 0 V 10kΩ 17 19 R12 0 z 0 10kΩ C 100kΩ 0 -z
R23 C4 10kΩ 10nF R22 U1D R26 4 A4 y R24 U2D Y 10kΩ 3 5 10kΩ A5 10kΩ 2 X 1 Y 7 0 A U3D 0 R25 X 10 6 0.1 V/V 0 V y 33.3kΩ 0.1 V/V 0 V R27 0 C -x 50kΩ
Figure 4
-5/15- 31 Jul 2020
R1 R21 C1 R4 A1 x y Y 21.7kΩ 10kΩ 10nF 10kΩ R2 U1A 13 11 U2A 3 16 R20 X -z 18 1kΩ U3A 10kΩ 20 R15 22 0.1 V/V 0 V R3 0 0 x 10kΩ A 100kΩ 0 -x 2020101601
R5 R19 C2 A2 -y R9 z Y 8.3kΩ 10kΩ 10nF U1B 10kΩ 6 R6 2 x X
1kΩ U2B 7 10 R18 9 0.1 V/V 0 V R7 U3B 0 10kΩ 15 R8 8 B 100kΩ y 10kΩ 0 0 -y
R10 5 R17 C3 -z R14 A3 20kΩ 10kΩ y Y 10nF 10kΩ U1C x X 21 R11 1 U2C 1kΩ 24 R16 23 R13 U3C 0.1 V/V 0 V 10kΩ 17 19 R12 0 z 0 10kΩ -x 100kΩ 0 -z
R30
10kΩ 8 R28 U4D 15 7 A6 50kΩ -z Y 0 B R23 X 13 R29 C4 33.3kΩ 10kΩ 0.1 V/V 0 V 10nF R22 U1d R26 3 A4 y R24 U2D Y 10kΩ 2 4 10kΩ A5 10kΩ 1 X 14 Y 6 0 A U3D 0 R25 X 11 5 0.1 V/V 0 V y 33.3kΩ 0.1 V/V 0 V R27 0 A 17 50kΩ
Figure 5
-6/15- 31 Jul 2020
R1 R21 C1 R4 A1 x y Y 21.7kΩ 10kΩ 10nF 10kΩ R2 U1A 13 11 U2A 3 16 R20 X -z 18 1kΩ U3A 10kΩ 20 R15 22 0.1 V/V 0 V R3 0 0 x 10kΩ A 100kΩ 0 -x 2020101601
R5 R19 C2 A2 -y R9 z Y 8.3kΩ 10kΩ 10nF U1B 10kΩ 6 R6 2 x X
1kΩ U2B 7 10 R18 9 0.1 V/V 0 V U3B R12 0 10kΩ 15 R8 8 -z y 10kΩ 100kΩ 0 0 -y
R10 5 R17 C3 -z R14 A3 20kΩ 10kΩ y Y 10nF 10kΩ U1C x X 21 R11 1 U2C 1kΩ 24 R16 23 R13 U3C 0.1 V/V 0 V 10kΩ 17 19 R12 0 z 0 10kΩ C 100kΩ 0 -z
R30
10kΩ 8 R28 U4D 15 7 A6 50kΩ -x Y 0 C R23 X 13 R29 C4 33.3kΩ 10kΩ 0.1 V/V 0 V 10nF R22 U1d R26 3 A4 y R24 U2D Y 10kΩ 2 4 10kΩ A5 10kΩ 1 X 14 Y 6 0 A U3D 0 R25 X 11 5 0.1 V/V 0 V y 33.3kΩ 0.1 V/V 0 V R27 0 A 17 50kΩ
Figure 6
-7/15- 31 Jul 2020
R1 R21 C1 R4 A1 x y Y 21.7kΩ 10kΩ 10nF 10kΩ R2 U1A 13 11 U2A 3 16 R20 X -z 18 1kΩ U3A 10kΩ 20 R15 22 0.1 V/V 0 V R3 0 0 x 10kΩ y 100kΩ 0 -x 2020101601
R5 R19 C2 A2 -y R9 z Y 8.3kΩ 10kΩ 10nF U1B 10kΩ 6 R6 2 x X
1kΩ U2B 7 10 R18 9 0.1 V/V 0 V R7 U3B 0 10kΩ 15 R8 8 B 100kΩ y 10kΩ 0 0 -y
R10 5 R17 C3 -z R14 A3 20kΩ 10kΩ y Y 10nF 10kΩ U1C x X 21 R11 1 U2C 1kΩ 24 R16 23 R13 U3C 0.1 V/V 0 V 10kΩ 17 19 R12 0 z 0 10kΩ C 100kΩ 0 -z
R30
10kΩ 8 R28 U4D 15 7 A6 50kΩ -x Y 0 C R23 X 13 R29 C4 33.3kΩ 10kΩ 0.1 V/V 0 V 10nF R22 U1d R26 3 A4 y R24 U2D Y 10kΩ 2 4 10kΩ A5 10kΩ 1 X 14 Y 6 0 A U3D 0 R25 X 11 5 0.1 V/V 0 V -z 33.3kΩ 0.1 V/V 0 V R27 0 B 17 50kΩ
Figure 7
-8/15- 31 Jul 2020
R1 R21 C1 R4 A1 x y Y 21.7kΩ 10kΩ 10nF 10kΩ R2 U1A 13 11 U2A 3 16 R20 X -z 18 1kΩ U3A 10kΩ 20 R15 22 0.1 V/V 0 V R3 0 0 x 10kΩ A 100kΩ 0 -x 2020101601
R5 R19 C2 A2 -y R9 z Y 8.3kΩ 10kΩ 10nF U1B 10kΩ 6 R6 2 x X
1kΩ U2B 7 10 R18 9 0.1 V/V 0 V R7 U3B 0 10kΩ 15 R8 8 B 100kΩ y 10kΩ 0 0 -y
R10 5 R17 C3 -z R14 A3 20kΩ 10kΩ y Y 10nF 10kΩ U1C x X 21 R11 1 U2C 1kΩ 24 R16 23 R13 U3C 0.1 V/V 0 V 10kΩ 17 19 R12 0 z 0 10kΩ C 100kΩ 0 -z
R30
10kΩ 6 R28 U4D 5 A6 50kΩ -z 10 Y
R29 0 B R23 X 9 C4 33.3kΩ 10kΩ 0.1 V/V 0 V 10nF R22 U1D R26 8 A4 y R24 U2D Y 10kΩ 7 16 10kΩ A5 10kΩ 3 X Y 21 0 A U3D 0 R25 12 X 4 20 0.1 V/V 0 V y 33.3kΩ 0.1 V/V 0 V R27 0 A 2 50kΩ
R33
A7 10kΩ Y 22 R31 U5D 11 X 1 17 -X 33.3kΩ 0.1 V/V 0 V R32 0 C 50kΩ
Figure 8
-9/15-
Figure 9
-10/15-
Figure 10
-11/15-
Figure 11
-12/15-
Figure 12
-13/15-
Figure 13
-14/15-
Figure 14
-15/15- 31 Jul 2020
R1 R21 C1 x R4 21.7kΩ 10kΩ A3 10nF 7 10kΩ y Y 3 4 IC=0.1V R2 11 U1A 5 V6 1 8 -z X 11 U2A 12 V 2020101601
2 R20 1kΩ 2 1 2 11 U3A 0 0.1 V/V 0 V R15 6 A4 R3 10kΩ 03 1 2 y Y 4 LF347BD 03 10kΩ 20 100kΩ 1 V5 0 X 4 LF347BD 3 12 V 9 4 LF347BD 0.1 V/V 0 V
A3 R5 R19 C2 R9 z Y -y 6 8.3kΩ 10kΩ x X U1B 10nF 10kΩ R6 2 IC=0.1V 0.1 V/V 0 V 1kΩ U2B 7 10 R18 9 R7 U3B A4 0 10kΩ 15 R8 8 -z Y 100kΩ 0 10kΩ X 11 0
0.1 V/V 0 V
R10 R17 C3 -z 5 R14 A5 20kΩ 10kΩ 10nF y Y IC=0.1V 10kΩ U1C x X 21 R11 1 U2C 1kΩ 24 R16 23 R13 U3C 0.1 V/V 0 V 10kΩ 17 19 A6 R12 0 0 10kΩ -x Y 3 100kΩ 0 X
0.1 V/V 0 V
Figure 15
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| CN113872749A (en) * | 2021-09-29 | 2021-12-31 | 南开大学 | System and circuit with 4 cluster of conservative chaotic streams |
| CN114095146A (en) * | 2021-11-26 | 2022-02-25 | 江苏科技大学 | Chaotic fractional order encryption circuit |
| CN115914487A (en) * | 2022-11-30 | 2023-04-04 | 湖南第一师范学院 | Image encryption method based on four-dimensional memristor chaotic system |
| CN116707514A (en) * | 2023-08-09 | 2023-09-05 | 苏州浪潮智能科技有限公司 | Multi-output memristor equivalent circuit, application system and control method |
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2020
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| CN113872749A (en) * | 2021-09-29 | 2021-12-31 | 南开大学 | System and circuit with 4 cluster of conservative chaotic streams |
| CN113872749B (en) * | 2021-09-29 | 2023-12-29 | 南开大学 | System with 4 clusters of conserved chaotic streams |
| CN114095146A (en) * | 2021-11-26 | 2022-02-25 | 江苏科技大学 | Chaotic fractional order encryption circuit |
| CN114095146B (en) * | 2021-11-26 | 2023-12-19 | 江苏科技大学 | Chaotic fractional order encryption circuit |
| CN115914487A (en) * | 2022-11-30 | 2023-04-04 | 湖南第一师范学院 | Image encryption method based on four-dimensional memristor chaotic system |
| CN115914487B (en) * | 2022-11-30 | 2024-04-26 | 湖南第一师范学院 | Image encryption method based on four-dimensional memristor chaotic system |
| CN116707514A (en) * | 2023-08-09 | 2023-09-05 | 苏州浪潮智能科技有限公司 | Multi-output memristor equivalent circuit, application system and control method |
| CN116707514B (en) * | 2023-08-09 | 2023-11-03 | 苏州浪潮智能科技有限公司 | Multi-output memristor equivalent circuit, application system and control method |
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