S&F Ref: 832944 AUSTRALIA PATENTS ACT 1990 COMPLETE SPECIFICATION FOR A STANDARD PATENT Name and Address Canon Kabushiki Kaisha, of 30-2, Shimomaruko 3-chome, of Applicant : Ohta-ku, Tokyo, 146, Japan Actual Inventor(s): Michael Chun Tao Chan, Stephen Farrar Address for Service: Spruson & Ferguson St Martins Tower Level 35 31 Market Street Sydney NSW 2000 (CCN 3710000177) Invention Title: Reliable error detection and error correction encoding for very small block lengths The following statement is a full description of this invention, including the best method of performing it known to me/us: 5845e(1045811 1) -1 RELIABLE ERROR DETECTION AND ERROR CORRECTION ENCODING FOR VERY SMALL BLOCK LENGTHS FIELD OF INVENTION The current invention relates to error detection and error correction for achieving reliable transmission of digital data over a noisy channel and in particular, reliable transmission of digital data of very small block lengths. 5 DESCRIPTION OF BACKGROUND ART The class of error correction codes that this invention is related to are low density parity check codes or LDPC codes. These codes were first proposed by Robert G. Gallager in 1963 and are well known for their superior performance compared to other codes such as in 10 terms of supporting data transmission rates approaching the theoretical Shannon limit. Traditional methods of constructing LDPC codes fall into two main categories, namely, pseudorandom techniques and combinatorial approaches. Recently, finite geometry based construction of LDPC codes has been published in the literature, and in particular, Y. Kou et. al. presented a method of constructing Euclidean Geometry LDPC codes or EG-LDPC 15 codes. These EG-LDPC codes typically have superior performance over pseudorandom LDPC codes and have well defined properties like minimum Hamming distances. One disadvantage that EG-LDPC codes have is that the set of possible block lengths that can be used are rather limited since the codes are constructed based on finite geometries. Methods have been proposed which expands the set of possible block lengths by taking a 20 base EG-LDPC code and performing either an extending or shortening operation on it to produce new EG-LDPC codes. On rare occasions during LDPC decoding via a belief propagation decoder, the result can incorrectly converge to an incorrect codeword, commonly the zero codeword, which itself is a valid input sequence. Experimentally, this often occurs when there is substantial 25 noise in the channel which leaves the received signal near the edge of decodability. When this occurs, there is no way to identify whether or not incorrect decoding occurred from the output of the LDPC decoder. There is a need for an efficient and reliable method of encoding to prevent such occurrences from happening at the decoder. Existing methods 1045250 832944_speci -2 indirectly solve this problem by using concatenated codes where there are at least two stages of error correction coding and one level of error detection coding. These methods have the disadvantage of being inefficient in achieving the goal of the present invention. They also do not specifically address very short block lengths, such as block lengths less 5 than 256 bits, by taking advantage of shortened EG-LDPC codes. The current invention addresses the shortfalls of these existing techniques. SUMMARY OF THE INVENTION The present invention pertains to a reliable error detection and error correction coding 10 scheme for very small block lengths. A cyclic redundancy check (CRC) code is calculated for a data payload to be transmitted reliably. This CRC code is concatenated to the data payload to form a concatenated message. Then, a bitwise XOR operation is performed on the concatenated message with a pseudorandom sequence of the same length to produce a randomised message. Finally, the randomised message is encoded using a suitable LDPC 15 code, typically a shortened EG-LDPC code. This encoded message is ready for modulation and transmission over the desired channel. In another aspect of the invention, a method of shortening a base finite geometry LDPC code to expand the set of available codes with new shortened codes of various block lengths and code rates is presented. The parity check matrix of a base finite geometry 20 LDPC code is taken. The number of lines to delete from the finite geometry is decided. Then, the rows corresponding to the lines to delete are removed from the parity check matrix. Also, the columns corresponding to the points that lie on these lines are removed from the parity check matrix. Further removal of points and lines from the geometry give rise to a larger set of available shortened finite geometry LDPC codes. 25 Thus, according to one aspect of the invention, there is provided a method for facilitating correct decoding of a small length input data payload by way of error detection and/or error correction encoding, the method comprising; e calculating and appending a cyclic redundancy check (CRC) code for the input data payload to form a concatenated message; 1045250 832944_speci -3 " performing a bitwise XOR operation between the concatenated message and a pseudorandom sequence of the same length to produce a randomised message; and * encoding the randomised message with a suitable LDPC code. 5 Preferably, the process of LDPC encoding is effected by calculation of the parity bits via an inverse matrix method. Also preferably, the encoded data is phase-modulated onto dots on a regular two dimensional grid. Also in a preferred embodiment, the block length of the code is less than 256 bits. 10 Also preferably, the randomised message is encoded with an LDPC code, the LDPC code being constructed by; * taking a suitable base Euclidean geometry low density parity check (EG-LDPC) code; and * undergoing a code shortening operation involving manipulation of the code's 15 parity check matrix to produce a shortened code of desired block length and code rate. Even more preferably, in the above mentioned embodiment, the base EG-LDPC code is based on Euclidean geometry EG(2,2 4 ). According to a second aspect of the invention, there is provided a method of error 20 detection and/or error correction decoding, the method comprising: e performing LDPC decoding on a received signal; 1045250 832944_speci -4 * reporting a decoding failure, if step (a) fails to decode, or, if decoding succeeds, performing a bitwise XOR operation between the decoded message and the pseudorandom message used for encoding, to produce a concatenated message; * splitting the concatenated message into its data payload and CRC parts; 5 e performing a CRC check between the data payload and the CRC; and " reporting a decoding failure if the CRC check fails in step (d). If the CRC check succeeds, then returning the data payload. According to a third aspect of the invention, there is provided method of deriving a shortened finite geometry LDPC code, the method comprising; 10 e constructing a parity check matrix for a base finite geometry LDPC code derived from a corresponding finite geometry; * selecting a number of lines to delete from the finite geometry; * removing the rows corresponding to the lines to delete in step (b), from the parity check matrix; 15 e removing the columns corresponding to points that lie on those lines identified in step (b), from the parity check matrix; * selecting a number of points to delete from the remaining finite geometry; * removing the columns corresponding to the points to delete identified in step (e), from the parity check matrix. 20 Preferably, there is an additional step of removing the rows corresponding to the lines that intersect the points identified in step (e), from the parity check matrix. 1045250 832944_speci -5 BRIEF DESCRIPTION OF THE DRAWINGS One or more embodiments of the invention will now be described with reference to the following drawings, in which: Fig. I is a block diagram of the processing stages involved with data encoding; 5 Fig. 2 is a schematic flow diagram illustrating a method of shortening an EG-LDPC code; Fig. 3 is a schematic flow diagram illustrating an extension over the method in Fig. 2 of shortening an EG-LDPC code; Fig. 4 is a schematic flow diagram illustrating another extension over the method in 10 Fig. 2 of shortening an EG-LDPC code; Fig. 5 is a flowchart showing the steps for reliable decoding; Fig. 6 is an example of a modulation and transmission scheme of digital data on printed media; Fig. 7 shows a modulated grid of dots used for encoding data in our barcode; 15 Fig. 8 shows how the modulated grid of dots is viewed conceptually for encoding and decoding purposes; Fig. 9 shows how data is encoded into the modulation of a single dot; Fig. 10 is a detailed view of the encoding scheme used to encode data into the modulation of a single dot; 20 Fig. 11 shows the encoding and decoding order of the data dots; Fig. 12 shows the tiling scheme used for our barcode; and Fig. 13 is a schematic block diagram of a general purpose computer upon which the described arrangements can be practiced. 25 DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION The present invention relates to the design of a reliable error detection and error correction coding scheme for very small block lengths and in particular, addresses the detection of incorrect LDPC decoding where the decoding converges to an incorrect codeword. Block diagram [100] in Fig. I shows the overall architecture of the present 30 invention. In block [110], the input data payload to be transmitted is taken and a cyclic redundancy check (CRC) is calculated for and concatenated to it. The output of block [110] 1045250 832944_speci -6 is input to block [120], where a bitwise XOR operation with a pseudorandom sequence of the same length is then applied. Finally, the output of block [120] is input into block [130] and encoded using a suitable shortened EG-LDPC code. The output of block [130] is ready for modulation and transmission over a desired channel. The description that follows 5 presents the preferred way to carry out the present invention and provide detailed explanation of the advantages of the present invention. Error Correction The design of error correction codes suitable for small block lengths is described below. 10 The advantages of using LDPC and in particular EG-LDPC codes are attractive because of its superior performance over pseudorandom LDPC codes. However, there is only a limited set of possible block lengths for EG-LDPC codes. One way to overcome this limitation is to perform extension or shortening of existing EG-LDPC codes to produce new ones. In order to appreciate how this is performed, a brief overview of EG-LDPC codes is 15 necessary. LDPC codes are a subset of linear block codes and the design of LDPC codes is based on the construction of a parity check matrix H inZ 2 as is well known to those skilled in the art. In particular, this parity check matrix must satisfy the following conditions: (1) each row consists of p "ones"; (2) each column consists of y "ones"; (3) the number of 20 ones in common between any two columns is no greater than 1; (4) both p and r are small compared to the length of the code and the number of rows in H. This last condition ensures that H has a small density of "ones" which gives it the name of LDPC code. If not all the columns or all the rows of the parity check matrix H have the same number of "ones", an LDPC code is said to be irregular. 25 The construction of EG-LDPC codes is based on finite geometries, specifically, Euclidean geometries denoted by EG(h,2'), which means a h -dimensional Euclidean geometry over a Galois Field GF(2'). The 2D EG-LDPC codes which are particularly interesting are based on Euclidean geometry EG(2,2') and is abbreviated as EG(s). If we denote the EG-LDPC parity check matrix as HEG , then a row in H EG represents a line in 30 the geometry and is called an incidence vector, where points corresponding to positions 1045250 832944 speci -7 where there are "ones" lie on the line. A column in H EG represents a point and is called an intersecting vector, where lines corresponding to positions where there are "ones" intersect the point. To construct the matrix H EG , a single line from EG(2,2') is taken and its incidence vector is constructed. This incidence vector is circularly shifted 22' - 2 times to 5 produce the remaining incidence vectors that make up the (22 - 1) x (22' -1) parity check matrix H EG The null space of H EG contains the EG-LDPC code. An example parity check matrix H EG for s = 2 is 0 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 1 1 0 0 0 1 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 1 HEG=1 01000100000001 1 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 1 01 The table below shows the first four in the set of Type I 2D EG-LDPC codes (Type II 10 codes are codes with parity check matrix H 2 = H,, , which are identical to Type I codes for 2D EG-LDPC codes), where n is the block length, k is the encoded message length and dne is the minimum Hamming distance. According to Massey, EG-LDPC codes are self-orthogonal codes where no two information symbols appear together in more than one parity check equation. Thus, if each information symbol in such a code is checked by at 15 least d -1I parity checks, then the minimum Hamming distance between codewords is at least d . In other words, the minimum Hamming distance of EG-LDPC codes are lower 1045250 832944_speci -8 bounded by the smallest number of "ones" in any column in H EG , which can be readily deduced. s n k dk P r 2 15 7 5 4 4 3 63 37 9 8 8 4 255 175 17 16 16 5 1023 781 33 32 32 From this table, it can be observed that the available block lengths n are few and the 5 available code rates are limited. This limits the use of these codes in many situations. In particular, the present invention is interested in small block lengths less than 256 bits. One technique to make available more codes with various block lengths and code rates is to take one of the existing EG-LDPC codes and apply an extending or shortening process on it. Although the description below uses Euclidean geometry based LDPC codes, it is also 10 possible to apply the same concepts to other finite geometry based LDPC codes such as projective geometry LDPC (PG-LDPC). Below is a description of a code shortening process. Conceptually, it involves removing all the points and lines that belong to a (h -1) -dimensional subspace EG(h - 1,2') from geometry EG(h,2'). For 2D EG-LDPC, the subspaces concerned are lines, and the code 15 shortening process corresponds to removing from the geometry a set of lines and the points that lie on these lines. Suppose we start with a Type I EG-LDPC parity check matrix denoted H() (2,s). The process of shortening the code is shown in the process [200] in Fig. 2. Firstly, before the process is started, the number of lines to delete from the geometry must be decided. This becomes a parameter that is used to generate a range of shortened 20 codes with various block lengths and code rates. Assuming the number of lines to delete 1 is determined. The selection of the 1 lines is arbitrary. Then, the process of code shortening begins at [210]. In step [220], the rows or incidence vectors in the parity check matrix that corresponds to the I lines that were marked to be deleted are identified. The columns or 1045250 832944_speci -9 intersecting vectors in the parity check matrix which correspond to the points that lie on these lines are identified in step [230]. Finally in step [240], all the rows and columns that were identified in steps [220] and [230] are removed from the parity check matrix and the resulting parity check matrix corresponds to the shortened EG-LDPC code. The process 5 finishes at step [250]. This process produces new codes which have at least the same minimum Hamming distance as the original code. An extension to the shortening process [200] in Fig. 2 is shown in process [300] in Fig. 3. Once again, before the process is started a number of lines to delete from the geometry must be decided. Suppose we assume the number of lines to delete 1 is determined. In 10 addition, a number of points to delete from the geometry must also be decided. Suppose we assume the number of points to delete p is determined. The quantities 1 and p become parameters into this code shortening process to generate a range of codes with various block lengths and code rates. The code shortening process [300] begins at [310]. The process [200] of Fig. 2 described previously is executed. Then in step [320], the columns in 15 the parity check matrix which correspond to the p points that were marked for deletion are identified. The selection of the p points is arbitrary. Finally in step [330], the columns identified in step [320] are removed from the parity check matrix and the resulting matrix corresponds to the shortened EG-LDPC code. The process finishes at step [340]. This process produces new codes which have at least the same minimum Hamming distance as 20 the original code. Some example codes using base EG-LDPC code EG(4) generated using this method is shown in the table below. Codes generated using the original shortening process [200] in Fig. 2 correspond to those in column p = 0. Code P (n,k) 0 1 2 3 4 0 255,175 254, 174 253, 173 252, 172 251, 171 1 239,160 238, 159 237, 158 236, 157 235, 156 1 2 223,145 222, 144 221, 143 220, 142 219, 141 3 207, 130 206, 129 205, 128 204, 127 203, 126 4 191,115 190,114 189,113 188,112 187,111 1045250 832944_speci -10 Yet another extension to the code shortening process [200] in Fig. 2 is shown in process [400] in Fig. 4. In this extension, the requirement of maintaining at least the same minimum Hamming distance as the original code is relaxed. Before the process is started, a 5 number of lines to delete from the geometry must be decided. Suppose we assume the number of lines to delete I is determined. The selection of the I lines is arbitrary. In addition, a number of points to delete from the geometry must also be decided. Suppose we assume the number of points to delete p is determined. The selection of the p points is arbitrary. The quantities 1 and p become parameters into the code shortening process to 10 generate a range of codes with various block lengths and code rates. The code shortening process [400] begins at [410]. The process [200] in Fig. 2 described previously is executed. Then in step [420], the columns in the parity check matrix which correspond to the p points that were marked for deletion are identified. The rows in the parity check matrix which correspond to the lines that intersect these points are identified in step [430]. Finally 15 in step [440], all the rows and columns that were identified in steps [420] and [430] are removed from the parity check matrix and the resulting matrix corresponds to the shortened EG-LDPC code. The process finishes at step [450]. The minimum Hamming distance of these shortened codes is typically less than that of the base code it was derived from but they provide more choice in selecting a code with a suitable block length and/or code rate. 20 Nevertheless, under experimental simulations, these EG-LDPC codes tend to outperform those generated using pseudorandom techniques of the same block length and code rate. Some example codes using base EG-LDPC code EG(4) generated using this method is shown in the table below. Code p (n,k) 0 1 2 3 4 0 255, 175 254, 175 253,175 252, 175 251,175 1 239, 160 238, 160 237,160 236, 160 235,160 1 2 223, 145 222, 145 221,145 220, 145 219,145 3 207,130 206, 130 205,130 204,130 203,130 1045250 832944_speci -11 4 191,115 190,115 189,115 188,115 187,115 d 17 16 15 14 13 Once a suitable code has been constructed, encoding of data can proceed. Firstly, the constructed parity check matrix H EG contains m = n - k linearly independent rows and in order to perform encoding, the linearly dependent rows must be removed. Well known 5 algorithms such as LU decomposition exists which perform such operations. The resultant matrix after removing the linearly dependent rows is denoted H. LDPC encoding involves producing codewords of block length n consisting of k unaltered message bits corresponding to the message to encode and an additional m check bits. If t represents a valid n -vector codeword, it must satisfy the following parity check condition in Z 2 : 10 H-t=0 where H is an m x n matrix in Z 2 . Each row in matrix H describes a parity check. This equation can be written with vector t split into message vector k and parity check vector m. Thus, the parity check condition becomes H]= 0. k 15 This equation can be equivalently expressed as Hm+Hkk =0 m=H-H kk where H, are the left m columns of H and Hk are the right k columns of H. Typically, calculating the product Hkk is fast because H, is a sparse matrix. However, H;' is potentially dense thus calculating the parity check vector m is generally slow. There 20 are some advanced techniques presented in the literature which attempt to increase the efficiency of this calculation. However, for the block lengths that the present invention is concerned with, the direct calculation of m according to the above equation will not adversely affect the performance of the encoder significantly. The matrix H;'Hk is constant with respect to the message vector k so this can be pre-calculated once before 1045250 832944_speci -12 encoding. We will refer to such an encoding method as an inverse matrix method, the name referring to a direct calculation of the inverse of matrix H,,,. Error Detection 5 In rare situations during LDPC decoding via a belief propagation decoder, the result has been observed to converge to an incorrect codeword, commonly the zero codeword, which itself is valid. This happens when a corrupted codeword is close to a valid codeword other than the correct codeword and the decoder returns the message that corresponds to the other codeword. To solve this problem, error detection techniques can be used to check 10 whether incorrect decoding occurred. A cyclic redundancy check (CRC) could be calculated and concatenated to the input data payload to make up a concatenated message and used for error correction coding using LDPC. However, this still does not completely solve the problem. The case when LDPC decodes incorrectly to the zero codeword remains problematic. When this occurs, both the received data payload and CRC become zero 15 polynomials, so it passes the cyclic redundancy check even though LDPC decoded to an incorrect codeword. To avoid this problem, a bitwise XOR operation with a pseudorandom sequence of the same length is performed on the concatenated sequence before the LDPC encoding stage. These steps are summarised in block diagram [100] in Fig. 1. Block [110] takes an input data payload and calculates and concatenates a CRC to the data payload to 20 produce a concatenated message. This becomes input to block [120], which performs a bitwise XOR operation between the concatenated message and a pseudorandom sequence of the same length, to produce a randomised message. This randomised message from block [120] is used as input to block [130] which performs LDPC encoding to produce an encoded message. The encoded message is ready for modulation and transmission over a 25 desired channel. This encoding process sets up the structure required for reliable error correction and detection during decoding. At the decoder, the reverse operation occurs as shown in diagram [500] in Fig. 5. The decoding process starts at step [510]. At step [520], LDPC decoding is attempted on the received message after transmission through a channel. A decision is made at [521], where if the decoding failed, step [570] is executed which 30 reports that the decoding failed. On the other hand, if decoding succeeded, step [530] is executed. A bitwise XOR operation is performed on the decoded message with the same 1045250 832944_speci -13 pseudorandom sequence that was used during the encoding process to undo the XOR operation performed during encoding. The output of this step is then passed onto step [540] which splits it into its data payload and CRC parts. A CRC check is performed whereby the data payload and CRC polynomials are checked against each other at step [550]. A decision 5 is made at [551], where if the CRC check fails, step [570] is executed which reports that the decoding failed. This means that the LDPC decoding converged to an incorrect codeword and is treated as a decoding failure. If, however, the CRC check was successful, then step [560] is executed. Here, the data payload is returned. Both steps [560] and [570] end the decoding process at [580]. 10 Applications One particular application where the block length and/or code rate is critical in the design of the error correction code is in the transmission of digital data on printed media. For example, the modulation technique used for transmission of digital data on printed 15 media may involve a regular grid of symbols. Certain spatial constraints on the arrangement of the symbols would place fixed limits on the block length of the error correction code. Furthermore, the required data capacity or required robustness against noise may place a constraint on the code rate of the error correction code. These concepts can be demonstrated with a simple example. Barcode [600] in Fig. 6 20 shows an example of a digital data transmission scheme suitable for printed media. It consists of a virtual grid [620] that is defined by virtual horizontal and vertical lines. The data symbols, one of which is shown in [610], are centred at the intersection of virtual lines [620]. In general, the data symbols can be any one taken from a set of N valid data symbols, which means that the storage capacity of a single data symbol is log 2 N bits of 25 raw information. In this example, there is a set of four distinct data symbols used in barcode [600], one of which is shown in [610]. This means that each symbol is capable of storing 2 bits of raw information. Furthermore, the barcode is constrained to a grid of 9 x 9 = 81 data symbols. This means, to design an error correction code for this digital data transmission scheme, the total amount of raw information bits cannot exceed 81 x 2 = 162 30 bits. Using process [300] in Fig. 3, a shortened code based on EG(4) with n = 162 and 1045250 832944_speci -14 k = 87 would be suitable for this channel. Thus, this code provides 87 bits of encoded data storage. The parameters used to generate this code using the extended shortening technique described in Fig. 3 are I = 5 and p = 13. This code is not available by using only process [200] in Fig. 2. The minimum Hamming distance of this code is 17, which is the same as 5 that of the base EG(4) code that it was derived from. In a preferred embodiment, a more elaborate scheme is used to store data in a barcode using a modulated grid of dots. Fig. 7 shows an enlarged view of the appearance of a modulated grid of dots. The modulated grid of dots consists of a large number of dots WBL02 and WBLO4 that lie close to or on the intersection points WBLO3 of a square 10 virtual grid WBLOI. Note that it is only the dots WBLO2 and WBLO4 that form the visible barcode, and the virtual regular grid WBLO3 is illustrated purely for explanation of the location of the dots WBLO2 and WBLO4. The barcode consists of two types of dots. The dot WBL02 is an example of a data dot this dot is modulated around an intersection point WBLO3. The dot WBLO4 is an example 15 of an alignment dot - this dot lies exactly on an intersection point WBL03. Data dots and alignment dots are shown with different shading in Fig. 7, but they are actually identical except for their modulation position; the shading is for illustrative purposes. In the preferred embodiment, the barcode consists of 50% data dots and 50% alignment dots in the arrangement shown in Fig. 7; of course other arrangements are possible with minimal 20 change. Fig. 8 shows the virtual grid discovered from barcode decoding. CELLO 1 is the discovered virtual grid, CELLO2 is a data dot and CELLO4 is an alignment dot. The alignment dots appear on each grid intersection point and are used to build the virtual grid CELLO 1. As the alignment dots are located at every second dot, the discovered virtual grid 25 is effectively offset by 45 degrees from the original square grid with a grid spacing a factor of \r larger. This discovered virtual grid divides the page into many square grid cells shown by CELLO3, where each grid cell contains exactly one data dot. Grid cells are the basic unit used for barcode data storage. Fig. 9 shows how information is stored in a data dot within a grid cell. The dot MOD02 30 lies close to the grid cell centre MOD05 corresponding to the grid cell which is part of the 1045250 832944_speci -15 virtual grid MODO1. The dot is modulated to one of eight possible positions, one of which is indicated by MOD03. The eight possible positions for each dot are arranged in a circle centred on the grid cell centre MOD05. The eight modulation positions are offset from the grid centre by a distance governed by the modulation quantum MOD04, herein referred to 5 as Mq. The value of Mq is chosen to be a fixed percentage of the original square grid spacing - a good choice for Mq is 40% of the original square grid spacing. This modulation method is a spatial analogy to phase modulation, well known in the telecommunications field. Fig. 10 shows the dot modulation positions in even greater detail; one of which is shown 10 as MOD03. They are phase modulated equally about the grid cell centre ZOOM03, and each modulation position such as ZOOMO1 has an associated digital code value ZOOM02, which is displayed as groups of three bits. The eight modulation positions (e.g. one is shown in position ZOOMO1) allow each dot to encode one of eight possible digital code values (for example, position ZOOMO1 encodes value ZOOM02). This allows a modulated 15 grid of dots to act as a digital data store, with each dot of the modulated grid storing one base-eight digit or octet of raw data. Ideally, each dot encodes a digital code value such that the dots are arranged in a Gray code in the circle. This facilitates error correction during decoding. In Fig. 10 starting clockwise from ZOOM02, the dots encode the values: 5, 7, 6, 2, 3, 1, 0 and 4 as octets. 20 The preferred method of serialising the data to be encoded onto the barcode is to firstly partition data into octets. Then, these digits can be written to a rectangular array of dots with the ordering shown in Fig. 11. This ordering starts at the topmost, leftmost grid cell ORDO1 and proceeds in the fast scan direction from left to right and the slow scan direction from top to bottom until the bottommost, rightmost grid cell ORD02 is reached. It 25 is of course possible to use other orderings. Fig. 12 shows a single unique barcode tile TILEOO and the tiling arrangement used. The barcode is then repeatedly tiled over the entire grid for redundancy. Logically, each barcode tile represents the data from two separate data channels: a high data density (herein referred to as HDD) channel and a low data density (herein referred to as LDD) channel. The HDD 30 channel has low robustness, while the LDD channel has high robustness. Spatially, the 1045250 832944_speci -16 barcode tile TILEOO is composed of four sub-tiles TILE01, TILE02, TILE03 and TILE04 herein referred to as HDD channel tiles. HDD channel tiles are square grids with dimensions of TILE14 (herein referred to as 'HDD tile size') in units of grid cells or data dots. Each HDD channel tile contains one smaller embedded tile herein referred to as an 5 LDD channel tile. The LDD channel tiles in the barcode tile are T[LE05, TILE06, TILE07 and TILE08. This means that the barcode tile TILEOO contains four copies of the LDD channel tile. Each LDD channel tile is a square grid with dimensions of TILE13 (herein referred to as 'LDD tile size') in units of grid cells or data dots. Additionally, the HDD channel occupies the full area of the four HDD channel tiles excluding the LDD channel 10 tiles, which means the barcode tile contains only a single copy of the HDD channel. For example, areas TILE09, TILE10, TILEl 1 and TILE12 collectively make up the HDD channel. The number of HDD channel tiles used to store the HDD channel can be expanded as required. Currently, barcode tile TILE0O uses a 2 x 2 arrangement of HDD channel tiles but it is possible to expand this to the next larger arrangement of a 15 3 x 3 arrangement of HDD channel tiles. Notice that this tiling scheme maintains a constant density of LDD channel tiles independent of the HDD channel arrangement used, thus providing a highly redundant and robust LDD channel. In order to provide highly reliable error correction and detection within the LDD and HDD channels, the present invention is applied. In this case, the LDD channel is the one 20 that is most applicable because high robustness and reliability is critical so a design for the LDD channel will be used to demonstrate the application of the present invention. The LDD tile size represents a spatial constraint applied to the barcode. The preferred value for LDD tile size is 8, which means there are 8 x 8 = 64 modulated data dots available to store raw data. Since each data dot can store three bits of raw data, the raw data capacity of the 25 LDD channel is 192 bits. A shortened code based on EG(4) with n = 191 and k = 115 would be suitable for this channel (one raw bit is unused). Of course, further analysis and experimentation with the actual channel that the barcode is transmitted through would need to be conducted to ensure that this code is suitable for its actual application. For the purpose of demonstration, suitability will be assumed. Thus, this code provides 115 bits of 30 encoded data storage. The parameters used to generate this code using the extended shortening technique described in Fig. 3 are I = 4 and p =0. The minimum Hamming 1045250 832944_speci -17 distance of this code is 17, which is the same as that of the base EG(4) code that it was derived from. An 11 -bit CRC, Ox64D in Koopman notation, is chosen to ensure against incorrect decoding. This CRC provides a Hamming distance of 4 for word lengths of 104 bits. Thus, after accounting for the CRC storage, the data payload size is 104 bits. 5 Hardware Implementation The hereinbefore described methods for error detection and error correction encoding and decoding may be implemented using a computer system 1300, such as that shown in Fig. 13, wherein the processes of Figs. 2 to 5 may be implemented as software, such as one 10 or more application programs executable within the computer system 1300. In particular, the various steps and sub-steps of the methods are effected by software instructions carried out within the computer system 1300. The instructions may be formed as one or more code modules, each for performing one or more particular tasks. The software may also be divided into two separate parts, in which a first part and the corresponding code modules 15 performs the described methods and a second part and the corresponding code modules manage a user interface between the first part and the user. The software may be stored in a computer readable medium, including the storage devices described below, for example. The software is loaded into the computer system 1300 from the computer readable medium, and then executed by the computer system 1300. A computer readable medium 20 having such software or computer program recorded on it is a computer program product. The use of the computer program product in the computer system 1300 preferably effects the described advantageous methods for error detection and error correction encoding and decoding. As seen in Fig. 13, the computer system 1300 is formed by a computer module 1301, 25 input devices such as a keyboard 1302 and a mouse pointer device 1303, and output devices including a printer 1315, a display device 1314 and loudspeakers 1317. An external Modulator-Demodulator (Modem) transceiver device 1316 may be used by the computer module 1301 for communicating to and from a communications network 1320 via a connection 1321. The network 1320 may be a wide-area network (WAN), such as the 30 Internet or a private WAN. Where the connection 1321 is a telephone line, the modem 1316 may be a traditional "dial-up" modem. Alternatively, where the connection 1321 is a 1045250 832944_speci -18 high capacity (eg: cable) connection, the modem 1316 may be a broadband modem. A wireless modem may also be used for wireless connection to the network 1320. The computer module 1301 typically includes at least one processor unit 1305, and a memory unit 1306 for example formed from semiconductor random access memory 5 (RAM) and read only memory (ROM). The module 1301 also includes an number of input/output (1/0) interfaces including an audio-video interface 1307 that couples to the video display 1314 and loudspeakers 1317, an I/O interface 1313 for the keyboard 1302 and mouse 1303 and optionally a joystick (not illustrated), and an interface 1308 for the external modem 1316 and printer 1315. In some implementations, the modem 1316 may 10 be incorporated within the computer module 1301, for example within the interface 1308. The computer module 1301 also has a local network interface 1311 which, via a connection 1323, permits coupling of the computer system 1300 to a local computer network 1322, known as a Local Area Network (LAN). As also illustrated, the local network 1322 may also couple to the wide network 1320 via a connection 1324, which would typically include 15 a so-called "firewall" device or similar functionality. The interface 1311 may be formed by an Ethernet circuit card, a wireless BluetoothTM or an IEEE 802.11 wireless arrangement. The interfaces 1308 and 1313 may afford both serial and parallel connectivity, the former typically being implemented according to the Universal Serial Bus (USB) standards and having corresponding USB connectors (not illustrated). Storage devices 1309 are 20 provided and typically include a hard disk drive (HDD) 1310. Other devices such as a floppy disk drive and a magnetic tape drive (not illustrated) may also be used. An optical disk drive 1312 is typically provided to act as a non-volatile source of data. Portable memory devices, such optical disks (eg: CD-ROM, DVD), USB-RAM, and floppy disks for example may then be used as appropriate sources of data to the system 1300. 25 The components 1305, to 1313 of the computer module 1301 typically communicate via an interconnected bus 1304 and in a manner which results in a conventional mode of operation of the computer system 1300 known to those in the relevant art. Examples of computers on which the described arrangements can be practised include IBM-PC's and compatibles, Sun Sparcstations, Apple MacTM or alike computer systems evolved 30 therefrom. 1045250 832944_speci -19 Typically, the application programs for implementing the discussed methods are resident on the hard disk drive 1310 and read and controlled in execution by the processor 1305. Intermediate storage of such programs and any data fetched from the networks 1320 and 1322 may be accomplished using the semiconductor memory 1306, 5 possibly in concert with the hard disk drive 1310. In some instances, the application programs may be supplied to the user encoded on one or more CD-ROM and read via the corresponding drive 1312, or alternatively may be read by the user from the networks 1320 or 1322. Still further, the software can also be loaded into the computer system 1300 from other computer readable media. Computer readable media refers to any storage medium 10 that participates in providing instructions and/or data to the computer system 1300 for execution and/or processing. Examples of such media include floppy disks, magnetic tape, CD-ROM, a hard disk drive, a ROM or integrated circuit, a magneto-optical disk, or a computer readable card such as a PCMCIA card and the like, whether or not such devices are internal or external of the computer module 1301. Examples of computer readable 15 transmission media that may also participate in the provision of instructions and/or data include radio or infra-red transmission channels as well as a network connection to another computer or networked device, and the Internet or Intranets including e-mail transmissions and information recorded on Websites and the like. The second part of the application programs and the corresponding code modules 20 mentioned above may be executed to implement one or more graphical user interfaces (GUIs) to be rendered or otherwise represented upon the display 1314. Through manipulation of the keyboard 1302 and the mouse 1303, a user of the computer system 1300 and the application may manipulate the interface to provide controlling commands and/or input to the applications associated with the GUI(s). 25 The methods for error detection and error correction encoding and decoding may alternatively be implemented in dedicated hardware such as one or more integrated circuits performing the steps and/or or sub steps of Figs. 2 to 5. Such dedicated hardware may include graphic processors, digital signal processors, or one or more microprocessors and associated memories. 30 The foregoing describes only some embodiments of the disclosed methods, and modifications and/or changes can be made thereto without departing from the scope and 1045250 832944_speci -20 spirit of the method, the embodiments being illustrative and not restrictive. For example, in some embodiments, the error correction functionality of the discussed methods may be optional and the methods may be primarily directed to error detection. 1045250 832944_speci