AU2003302261A1 - Method of electroplating copper over a patterned dielectric layer to enhance process uniformity of a subsequent cmp process - Google Patents

Method of electroplating copper over a patterned dielectric layer to enhance process uniformity of a subsequent cmp process

Info

Publication number
AU2003302261A1
AU2003302261A1 AU2003302261A AU2003302261A AU2003302261A1 AU 2003302261 A1 AU2003302261 A1 AU 2003302261A1 AU 2003302261 A AU2003302261 A AU 2003302261A AU 2003302261 A AU2003302261 A AU 2003302261A AU 2003302261 A1 AU2003302261 A1 AU 2003302261A1
Authority
AU
Australia
Prior art keywords
dielectric layer
patterned dielectric
electroplating copper
copper over
subsequent cmp
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2003302261A
Other languages
English (en)
Inventor
Gerd Franz Marxsen
Frank Mauersberger
Markus Nopper
Axel Preusse
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE10319135A external-priority patent/DE10319135B4/de
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of AU2003302261A1 publication Critical patent/AU2003302261A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Manufacturing Of Printed Wiring (AREA)
AU2003302261A 2003-04-28 2003-12-22 Method of electroplating copper over a patterned dielectric layer to enhance process uniformity of a subsequent cmp process Abandoned AU2003302261A1 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
DE10319135.6 2003-04-28
DE10319135A DE10319135B4 (de) 2003-04-28 2003-04-28 Verfahren zum Elektroplattieren von Kupfer über einer strukturierten dielektrischen Schicht, um die Prozess-Gleichförmigkeit eines nachfolgenden CMP-Prozesses zu verbessern
US10/666,195 2003-09-19
US10/666,195 US6958247B2 (en) 2003-04-28 2003-09-19 Method of electroplating copper over a patterned dielectric layer to enhance process uniformity of a subsequent CMP process
PCT/US2003/041181 WO2004097932A2 (en) 2003-04-28 2003-12-22 Method of electroplating copper over a patterned dielectric layer to enhance process uniformity of a subsequent cmp process

Publications (1)

Publication Number Publication Date
AU2003302261A1 true AU2003302261A1 (en) 2004-11-23

Family

ID=33419999

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2003302261A Abandoned AU2003302261A1 (en) 2003-04-28 2003-12-22 Method of electroplating copper over a patterned dielectric layer to enhance process uniformity of a subsequent cmp process

Country Status (5)

Country Link
JP (1) JP2006515467A (ko)
KR (1) KR101136139B1 (ko)
AU (1) AU2003302261A1 (ko)
GB (1) GB2418067B (ko)
WO (1) WO2004097932A2 (ko)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100761360B1 (ko) * 2006-03-29 2007-09-27 주식회사 하이닉스반도체 플래쉬 메모리 소자의 메탈 배선 제조 방법
WO2012103357A1 (en) * 2011-01-26 2012-08-02 Enthone Inc. Process for filling vias in the microelectronics
US20230279576A1 (en) * 2022-03-03 2023-09-07 Applied Materials, Inc. Plating and deplating currents for material co-planarity in semiconductor plating processes
US20230304183A1 (en) * 2022-03-22 2023-09-28 Applied Materials, Inc. Methods and apparatus for altering lithographic patterns to adjust plating uniformity

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2891161B2 (ja) 1996-02-15 1999-05-17 日本電気株式会社 配線形成方法
KR20000043909A (ko) * 1998-12-29 2000-07-15 김영환 반도체 소자의 금속배선 형성 방법
KR20000056852A (ko) * 1999-02-26 2000-09-15 로버트 에이치. 씨. 챠오 집적회로 내의 금속 상호연결 구조의 제조 방법
US6179691B1 (en) * 1999-08-06 2001-01-30 Taiwan Semiconductor Manufacturing Company Method for endpoint detection for copper CMP
US6350364B1 (en) * 2000-02-18 2002-02-26 Taiwan Semiconductor Manufacturing Company Method for improvement of planarity of electroplated copper
JP3797860B2 (ja) * 2000-09-27 2006-07-19 株式会社荏原製作所 めっき装置及びめっき方法
US6746589B2 (en) * 2000-09-20 2004-06-08 Ebara Corporation Plating method and plating apparatus
JP3725054B2 (ja) * 2000-09-20 2005-12-07 株式会社荏原製作所 基板の電解めっき方法および電解めっき装置
US6863795B2 (en) * 2001-03-23 2005-03-08 Interuniversitair Microelektronica Centrum (Imec) Multi-step method for metal deposition
JP2003068689A (ja) * 2001-08-22 2003-03-07 Tokyo Seimitsu Co Ltd フィードバック式研磨装置及び研磨方法
JP3807295B2 (ja) * 2001-11-30 2006-08-09 ソニー株式会社 研磨方法
JP2003277985A (ja) * 2002-03-20 2003-10-02 Fujitsu Ltd メッキ成膜方法及びメッキ成膜装置

Also Published As

Publication number Publication date
WO2004097932A2 (en) 2004-11-11
JP2006515467A (ja) 2006-05-25
GB2418067B (en) 2007-02-14
KR101136139B1 (ko) 2012-04-20
GB2418067A (en) 2006-03-15
GB0521254D0 (en) 2005-11-30
WO2004097932A3 (en) 2004-12-16
KR20060008946A (ko) 2006-01-27

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase