ATE548697T1 - Speichersystem und verfahren mit flüchtigen und nichtflüchtigen speicheranordnungen auf derselben hierarchischen ebene - Google Patents

Speichersystem und verfahren mit flüchtigen und nichtflüchtigen speicheranordnungen auf derselben hierarchischen ebene

Info

Publication number
ATE548697T1
ATE548697T1 AT07865361T AT07865361T ATE548697T1 AT E548697 T1 ATE548697 T1 AT E548697T1 AT 07865361 T AT07865361 T AT 07865361T AT 07865361 T AT07865361 T AT 07865361T AT E548697 T1 ATE548697 T1 AT E548697T1
Authority
AT
Austria
Prior art keywords
memory
dram
flash memory
volatile
processor
Prior art date
Application number
AT07865361T
Other languages
English (en)
Inventor
Dean Klein
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Application granted granted Critical
Publication of ATE548697T1 publication Critical patent/ATE548697T1/de

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B7/00—Recording or reproducing by optical means, e.g. recording using a thermal beam of optical radiation by modifying optical properties or the physical structure, reproducing using an optical beam at lower power by sensing optical properties; Record carriers therefor
    • G11B7/12—Heads, e.g. forming of the optical beam spot or modulation of the optical beam
    • G11B7/14—Heads, e.g. forming of the optical beam spot or modulation of the optical beam specially adapted to record on, or to reproduce from, more than one track simultaneously
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1684—Details of memory controller using multiple buses
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Computer Hardware Design (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Memory System (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Read Only Memory (AREA)
  • Static Random-Access Memory (AREA)
AT07865361T 2007-01-22 2007-12-07 Speichersystem und verfahren mit flüchtigen und nichtflüchtigen speicheranordnungen auf derselben hierarchischen ebene ATE548697T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/656,578 US7564722B2 (en) 2007-01-22 2007-01-22 Memory system and method having volatile and non-volatile memory devices at same hierarchical level
PCT/US2007/086740 WO2008091443A1 (en) 2007-01-22 2007-12-07 Memory system and method having volatile and non-volatile memory devices at same hierarchical level

Publications (1)

Publication Number Publication Date
ATE548697T1 true ATE548697T1 (de) 2012-03-15

Family

ID=39642364

Family Applications (1)

Application Number Title Priority Date Filing Date
AT07865361T ATE548697T1 (de) 2007-01-22 2007-12-07 Speichersystem und verfahren mit flüchtigen und nichtflüchtigen speicheranordnungen auf derselben hierarchischen ebene

Country Status (6)

Country Link
US (5) US7564722B2 (de)
EP (1) EP2126919B1 (de)
KR (1) KR101080498B1 (de)
CN (1) CN101573760B (de)
AT (1) ATE548697T1 (de)
WO (1) WO2008091443A1 (de)

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Also Published As

Publication number Publication date
EP2126919A1 (de) 2009-12-02
US20100306461A1 (en) 2010-12-02
KR20090102822A (ko) 2009-09-30
US7564722B2 (en) 2009-07-21
US20120297129A1 (en) 2012-11-22
US20090265509A1 (en) 2009-10-22
WO2008091443A1 (en) 2008-07-31
US20110167207A1 (en) 2011-07-07
CN101573760B (zh) 2012-10-03
KR101080498B1 (ko) 2011-11-04
US20080177923A1 (en) 2008-07-24
CN101573760A (zh) 2009-11-04
EP2126919A4 (de) 2010-12-22
US7916553B2 (en) 2011-03-29
EP2126919B1 (de) 2012-03-07
US8248861B2 (en) 2012-08-21
US7778092B2 (en) 2010-08-17
US8493797B2 (en) 2013-07-23

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