AT511188T - Vorrichtung und verfahren zum reparieren eines halbleiterspeichers - Google Patents

Vorrichtung und verfahren zum reparieren eines halbleiterspeichers

Info

Publication number
AT511188T
AT511188T AT06773191T AT06773191T AT511188T AT 511188 T AT511188 T AT 511188T AT 06773191 T AT06773191 T AT 06773191T AT 06773191 T AT06773191 T AT 06773191T AT 511188 T AT511188 T AT 511188T
Authority
AT
Austria
Prior art keywords
repairing
semiconductor memory
semiconductor
memory
Prior art date
Application number
AT06773191T
Other languages
English (en)
Inventor
Chris Martin
Troy Manning
Brent Keeth
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US11/170,260 priority Critical patent/US7215586B2/en
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Priority to PCT/US2006/023219 priority patent/WO2007005218A1/en
Publication of AT511188T publication Critical patent/AT511188T/de

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C17/00Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G11C17/165Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44Indication or identification of errors, e.g. for repair
    • G11C29/4401Indication or identification of errors, e.g. for repair for self repair
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70Masking faults in memories by using spares or by reconfiguring
    • G11C29/78Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/785Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
    • G11C29/789Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using non-volatile cells or latches
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70Masking faults in memories by using spares or by reconfiguring
    • G11C29/78Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/808Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a flexible replacement scheme
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/4402Internal storage of test result, quality data, chip identification, repair information
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70Masking faults in memories by using spares or by reconfiguring
    • G11C29/78Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/802Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout by encoding redundancy signals
AT06773191T 2005-06-29 2006-06-14 Vorrichtung und verfahren zum reparieren eines halbleiterspeichers AT511188T (de)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US11/170,260 US7215586B2 (en) 2005-06-29 2005-06-29 Apparatus and method for repairing a semiconductor memory
PCT/US2006/023219 WO2007005218A1 (en) 2005-06-29 2006-06-14 Apparatus and method for repairing a semiconductor memory

Publications (1)

Publication Number Publication Date
AT511188T true AT511188T (de) 2011-06-15

Family

ID=37192636

Family Applications (1)

Application Number Title Priority Date Filing Date
AT06773191T AT511188T (de) 2005-06-29 2006-06-14 Vorrichtung und verfahren zum reparieren eines halbleiterspeichers

Country Status (8)

Country Link
US (4) US7215586B2 (de)
EP (1) EP1911038B1 (de)
JP (1) JP5321883B2 (de)
KR (1) KR101317034B1 (de)
CN (1) CN101253576B (de)
AT (1) AT511188T (de)
TW (1) TWI317521B (de)
WO (1) WO2007005218A1 (de)

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US7609579B2 (en) * 2007-11-21 2009-10-27 Etron Technology Inc. Memory module with failed memory cell repair function and method thereof
US8254191B2 (en) 2008-10-30 2012-08-28 Micron Technology, Inc. Switched interface stacked-die memory architecture
JP2010146649A (ja) * 2008-12-19 2010-07-01 Elpida Memory Inc 半導体記憶装置
JP5559616B2 (ja) * 2010-06-17 2014-07-23 ラピスセミコンダクタ株式会社 半導体メモリ装置
KR101113790B1 (ko) 2010-10-15 2012-02-27 주식회사 하이닉스반도체 퓨즈 회로 및 이를 포함하는 메모리장치
KR101196907B1 (ko) * 2010-10-27 2012-11-05 에스케이하이닉스 주식회사 반도체 메모리 장치 및 그의 동작 방법
KR20130098039A (ko) 2012-02-27 2013-09-04 삼성전자주식회사 패키징 후에 발생되는 특성 결함을 구제하는 반도체 장치
US9165679B2 (en) * 2012-09-18 2015-10-20 Samsung Electronics Co., Ltd. Post package repairing method, method of preventing multiple activation of spare word lines, and semiconductor memory device including fuse programming circuit
KR102116364B1 (ko) 2013-11-18 2020-05-28 삼성전자주식회사 메모리 시스템 및 그에 따른 반도체 메모리의 결함 메모리 셀 관리방법
US9343184B2 (en) * 2014-04-07 2016-05-17 Micron Technology, Inc. Soft post package repair of memory devices
KR20160030717A (ko) * 2014-09-11 2016-03-21 에스케이하이닉스 주식회사 메모리 장치 및 이를 포함하는 메모리 시스템
KR102252376B1 (ko) 2014-12-08 2021-05-14 삼성전자주식회사 셀 특성 플래그를 이용하여 리프레쉬 동작을 제어하는 메모리 장치
KR102269899B1 (ko) 2015-01-12 2021-06-28 삼성전자주식회사 메모리 장치 및 이를 포함하는 메모리 시스템
US9666307B1 (en) 2016-09-14 2017-05-30 Micron Technology, Inc. Apparatuses and methods for flexible fuse transmission
US10276239B2 (en) * 2017-04-27 2019-04-30 Ememory Technology Inc. Memory cell and associated array structure
US10381103B2 (en) * 2017-08-18 2019-08-13 Micron Technology, Inc. Apparatuses and methods for latching redundancy repair addresses to avoid address bits overwritten at a repair block
US10443531B2 (en) 2017-08-18 2019-10-15 Micron Technology, Inc. Apparatuses and methods for storing redundancy repair information for memories
US10839934B2 (en) * 2018-05-30 2020-11-17 Arm Limited Redundancy circuitry for memory application
CN110033813A (zh) * 2018-08-31 2019-07-19 济南德欧雅安全技术有限公司 一种翻译器设备
US10832791B2 (en) 2019-01-24 2020-11-10 Micron Technology, Inc. Apparatuses and methods for soft post-package repair

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Also Published As

Publication number Publication date
WO2007005218B1 (en) 2007-04-26
US20070002646A1 (en) 2007-01-04
US7215586B2 (en) 2007-05-08
TW200715296A (en) 2007-04-16
US7408825B2 (en) 2008-08-05
KR101317034B1 (ko) 2013-10-11
US7492652B2 (en) 2009-02-17
CN101253576B (zh) 2014-06-18
WO2007005218A1 (en) 2007-01-11
JP5321883B2 (ja) 2013-10-23
KR20080028441A (ko) 2008-03-31
JP2009500780A (ja) 2009-01-08
TWI317521B (en) 2009-11-21
US7813194B2 (en) 2010-10-12
CN101253576A (zh) 2008-08-27
US20080037342A1 (en) 2008-02-14
US20070153595A1 (en) 2007-07-05
EP1911038B1 (de) 2011-05-25
US20090147600A1 (en) 2009-06-11
EP1911038A1 (de) 2008-04-16

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