AT507615T - Integrated circuit - Google Patents

Integrated circuit

Info

Publication number
AT507615T
AT507615T AT02718307T AT02718307T AT507615T AT 507615 T AT507615 T AT 507615T AT 02718307 T AT02718307 T AT 02718307T AT 02718307 T AT02718307 T AT 02718307T AT 507615 T AT507615 T AT 507615T
Authority
AT
Austria
Prior art keywords
integrated circuit
integrated
circuit
Prior art date
Application number
AT02718307T
Other languages
German (de)
Inventor
Stephen Maxwell Parkes
Original Assignee
Univ Dundee
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to GB0108807A priority Critical patent/GB2374242B/en
Application filed by Univ Dundee filed Critical Univ Dundee
Priority to PCT/GB2002/001407 priority patent/WO2002082653A2/en
Publication of AT507615T publication Critical patent/AT507615T/en

Links

Classifications

    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736Structural details of routing resources
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778Structural details for adapting physical parameters
    • H03K19/17784Structural details for adapting physical parameters for supply voltage
AT02718307T 2001-04-07 2002-03-27 Integrated circuit AT507615T (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
GB0108807A GB2374242B (en) 2001-04-07 2001-04-07 Integrated circuit and related improvements
PCT/GB2002/001407 WO2002082653A2 (en) 2001-04-07 2002-03-27 Integrated circuit

Publications (1)

Publication Number Publication Date
AT507615T true AT507615T (en) 2011-05-15

Family

ID=9912482

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02718307T AT507615T (en) 2001-04-07 2002-03-27 Integrated circuit

Country Status (7)

Country Link
US (1) US7012448B2 (en)
EP (1) EP1374403B1 (en)
AT (1) AT507615T (en)
AU (1) AU2002249377A1 (en)
DE (1) DE60239862D1 (en)
GB (1) GB2374242B (en)
WO (1) WO2002082653A2 (en)

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6605962B2 (en) * 2001-05-06 2003-08-12 Altera Corporation PLD architecture for flexible placement of IP function blocks
US6975139B2 (en) 2004-03-30 2005-12-13 Advantage Logic, Inc. Scalable non-blocking switching network for programmable logic
US7551564B2 (en) * 2004-05-28 2009-06-23 Intel Corporation Flow control method and apparatus for single packet arrival on a bidirectional ring interconnect
US20060080632A1 (en) * 2004-09-30 2006-04-13 Mathstar, Inc. Integrated circuit layout having rectilinear structure of objects
US20070247189A1 (en) * 2005-01-25 2007-10-25 Mathstar Field programmable semiconductor object array integrated circuit
EP1859575A1 (en) * 2005-03-04 2007-11-28 Philips Electronics N.V. Electronic device and a method for arbitrating shared resources
US7268581B1 (en) * 2005-04-21 2007-09-11 Xilinx, Inc. FPGA with time-multiplexed interconnect
US7451426B2 (en) * 2005-07-07 2008-11-11 Lsi Corporation Application specific configurable logic IP
CN100450067C (en) * 2005-11-18 2009-01-07 华为技术有限公司 Service apparatus exchange network and exchange method
US7568064B2 (en) * 2006-02-21 2009-07-28 M2000 Packet-oriented communication in reconfigurable circuit(s)
WO2008031851A1 (en) * 2006-09-13 2008-03-20 Ecole Polytechnique Federale De Lausanne (Epfl) Methods for hardware reduction and overall performance improvement in communication system
US20090144595A1 (en) * 2007-11-30 2009-06-04 Mathstar, Inc. Built-in self-testing (bist) of field programmable object arrays
US20100002581A1 (en) * 2008-04-04 2010-01-07 The Arizona Board Of Regents On Behalf Of The University Of Arizona Method for Inter-Router Dual-Function Energy- and Area-Efficient Links for Network-on-Chips
FR2933826B1 (en) * 2008-07-09 2011-11-18 Univ Paris Curie Programmable logic network, interconnect switch and logic unit for such a network
EP2541851A1 (en) * 2011-06-30 2013-01-02 Astrium Limited Apparatus and method for use in a spacewire-based network
US8629689B1 (en) * 2012-05-18 2014-01-14 Altera Corporation Integrated circuit with improved interconnect routing and associated methods
JP6029010B2 (en) * 2013-03-22 2016-11-24 大学共同利用機関法人情報・システム研究機構 Semiconductor chip, semiconductor chip connection system
US10331583B2 (en) 2013-09-26 2019-06-25 Intel Corporation Executing distributed memory operations using processing elements connected by distributed channels
US10126791B2 (en) * 2014-11-04 2018-11-13 Progranalog Corp. Configurable power management integrated circuit
US10402168B2 (en) 2016-10-01 2019-09-03 Intel Corporation Low energy consumption mantissa multiplication for floating point multiply-add operations
US10416999B2 (en) 2016-12-30 2019-09-17 Intel Corporation Processors, methods, and systems with a configurable spatial accelerator
US10474375B2 (en) 2016-12-30 2019-11-12 Intel Corporation Runtime address disambiguation in acceleration hardware
US10469397B2 (en) 2017-07-01 2019-11-05 Intel Corporation Processors and methods with configurable network-based dataflow operator circuits
US10445451B2 (en) 2017-07-01 2019-10-15 Intel Corporation Processors, methods, and systems for a configurable spatial accelerator with performance, correctness, and power reduction features
US10387319B2 (en) 2017-07-01 2019-08-20 Intel Corporation Processors, methods, and systems for a configurable spatial accelerator with memory system performance, power reduction, and atomics support features
US10445234B2 (en) 2017-07-01 2019-10-15 Intel Corporation Processors, methods, and systems for a configurable spatial accelerator with transactional and replay features
US10467183B2 (en) 2017-07-01 2019-11-05 Intel Corporation Processors and methods for pipelined runtime services in a spatial array
US10445098B2 (en) 2017-09-30 2019-10-15 Intel Corporation Processors and methods for privileged configuration in a spatial array
US10380063B2 (en) 2017-09-30 2019-08-13 Intel Corporation Processors, methods, and systems with a configurable spatial accelerator having a sequencer dataflow operator
US10445250B2 (en) 2017-12-30 2019-10-15 Intel Corporation Apparatus, methods, and systems with a configurable spatial accelerator
US20190205269A1 (en) * 2017-12-30 2019-07-04 Intel Corporation Apparatus, methods, and systems for multicast in a configurable spatial accelerator
US10417175B2 (en) 2017-12-30 2019-09-17 Intel Corporation Apparatus, methods, and systems for memory consistency in a configurable spatial accelerator
US10459866B1 (en) 2018-06-30 2019-10-29 Intel Corporation Apparatuses, methods, and systems for integrated control and data processing in a configurable spatial accelerator

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4569041A (en) * 1983-03-17 1986-02-04 Nec Corporation Integrated circuit/packet switching system
JPS6129687B2 (en) 1983-11-29 1986-07-08 Maekawa Seisakusho Kk
DE3702614A1 (en) * 1987-01-29 1988-08-11 Standard Elektrik Lorenz Ag Digital switching network for circuit and packet switching and coupling device for this purpose
JPH01255347A (en) * 1988-04-04 1989-10-12 Fujitsu Ltd Integrated circuit for parallel/serial-serial/parallel conversion
DE68924191D1 (en) * 1988-04-21 1995-10-19 Nec Corp For integrated circuit design suitable packet switching.
JP2723926B2 (en) * 1988-09-20 1998-03-09 川崎製鉄株式会社 Programmable Rojitsuku devices
US5212652A (en) * 1989-08-15 1993-05-18 Advanced Micro Devices, Inc. Programmable gate array with improved interconnect structure
JPH04151854A (en) * 1990-10-15 1992-05-25 Nec Ic Microcomput Syst Ltd Semiconductor integrated circuit device
US5483178A (en) * 1993-03-29 1996-01-09 Altera Corporation Programmable logic device with logic block outputs coupled to adjacent logic block output multiplexers
JPH06118141A (en) * 1992-10-05 1994-04-28 Hitachi Ltd Semiconductor integrated circuit device
US5457410A (en) * 1993-08-03 1995-10-10 Btr, Inc. Architecture and interconnect scheme for programmable logic circuits
US5682107A (en) * 1994-04-01 1997-10-28 Xilinx, Inc. FPGA architecture with repeatable tiles including routing matrices and logic matrices
US5815726A (en) * 1994-11-04 1998-09-29 Altera Corporation Coarse-grained look-up table architecture
US6072944A (en) 1995-09-08 2000-06-06 Iq Systems, Inc. Methods and apparatus for distributed processing and rapid ASIC development
US5880597A (en) * 1996-09-18 1999-03-09 Altera Corporation Interleaved interconnect for programmable logic array devices
US5880598A (en) * 1997-01-10 1999-03-09 Xilinx, Inc. Tile-based modular routing resources for high density programmable logic device
JPH10255347A (en) 1997-03-12 1998-09-25 Seiko Epson Corp Magneto-optical recording and reproducing device
EP0867820A3 (en) 1997-03-14 2000-08-16 Interuniversitair Micro-Elektronica Centrum Vzw A design environment and a method for generating an implementable description of a digital system
US6084429A (en) * 1998-04-24 2000-07-04 Xilinx, Inc. PLD having a window pane architecture with segmented and staggered interconnect wiring between logic block arrays
JP3255113B2 (en) * 1998-07-01 2002-02-12 日本電気株式会社 Packet switching system, integrated circuits, the packet switch control method comprising the same, the packet switch control program recording medium
US6191612B1 (en) * 1998-11-19 2001-02-20 Vantis Corporation Enhanced I/O control flexibility for generating control signals
JP2001127766A (en) * 1999-10-25 2001-05-11 Toshiba Corp Line interface and packet exchange
US7082484B2 (en) * 2001-01-16 2006-07-25 International Business Machines Corporation Architecture for advanced serial link between two cards

Also Published As

Publication number Publication date
DE60239862D1 (en) 2011-06-09
EP1374403B1 (en) 2011-04-27
WO2002082653A2 (en) 2002-10-17
US7012448B2 (en) 2006-03-14
GB2374242B (en) 2005-03-16
GB2374242A (en) 2002-10-09
US20040124877A1 (en) 2004-07-01
GB0108807D0 (en) 2001-05-30
AU2002249377A1 (en) 2002-10-21
EP1374403A2 (en) 2004-01-02
WO2002082653A3 (en) 2002-11-21

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Legal Events

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