AT507520T - Method and device for detecting gate characteristics in pipeline design electronic circuits - Google Patents

Method and device for detecting gate characteristics in pipeline design electronic circuits

Info

Publication number
AT507520T
AT507520T AT08787252T AT08787252T AT507520T AT 507520 T AT507520 T AT 507520T AT 08787252 T AT08787252 T AT 08787252T AT 08787252 T AT08787252 T AT 08787252T AT 507520 T AT507520 T AT 507520T
Authority
AT
Austria
Prior art keywords
pipeline
electronic circuits
detecting gate
gate
detecting
Prior art date
Application number
AT08787252T
Other languages
German (de)
Inventor
Matthew Fernsler
Hans Jacobson
Johny Srouji
Todd Swanson
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US11/842,491 priority Critical patent/US8073669B2/en
Application filed by Ibm filed Critical Ibm
Priority to PCT/EP2008/060722 priority patent/WO2009024540A2/en
Publication of AT507520T publication Critical patent/AT507520T/en

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 – G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power management, i.e. event-based initiation of power-saving mode
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 – G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power management, i.e. event-based initiation of power-saving mode
    • G06F1/3234Power saving characterised by the action undertaken
    • G06F1/3237Power saving characterised by the action undertaken by disabling clock generation or distribution
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3867Concurrent instruction execution, e.g. pipeline, look ahead using instruction pipelines
    • Y02D10/128
AT08787252T 2007-08-21 2008-08-14 Method and device for detecting gate characteristics in pipeline design electronic circuits AT507520T (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US11/842,491 US8073669B2 (en) 2007-08-21 2007-08-21 Method and apparatus for detecting clock gating opportunities in a pipelined electronic circuit design
PCT/EP2008/060722 WO2009024540A2 (en) 2007-08-21 2008-08-14 Method and apparatus for detecting clock gating opportunities in a pipelined electronic circuit design

Publications (1)

Publication Number Publication Date
AT507520T true AT507520T (en) 2011-05-15

Family

ID=40378739

Family Applications (1)

Application Number Title Priority Date Filing Date
AT08787252T AT507520T (en) 2007-08-21 2008-08-14 Method and device for detecting gate characteristics in pipeline design electronic circuits

Country Status (9)

Country Link
US (1) US8073669B2 (en)
EP (1) EP2179342B1 (en)
JP (1) JP5147944B2 (en)
KR (1) KR20100037628A (en)
CN (1) CN101779179B (en)
AT (1) AT507520T (en)
DE (1) DE602008006561D1 (en)
TW (1) TW200915724A (en)
WO (1) WO2009024540A2 (en)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2456363A (en) * 2008-01-08 2009-07-15 Ibm Methods and system for clock gating enhancement
US7844843B2 (en) * 2008-12-22 2010-11-30 International Business Machines Corporation Implementing power savings in HSS clock-gating circuit
US8302043B2 (en) * 2009-09-17 2012-10-30 International Business Machines Corporation Verification of logic circuit designs using dynamic clock gating
US9495490B2 (en) 2012-07-16 2016-11-15 International Business Machines Corporation Active power dissipation detection based on erroneus clock gating equations
US9916407B2 (en) 2013-12-05 2018-03-13 International Business Machines Corporation Phase algebra for analysis of hierarchical designs
US9268889B2 (en) * 2013-12-05 2016-02-23 International Business Machines Corporation Verification of asynchronous clock domain crossings
US10318695B2 (en) 2013-12-05 2019-06-11 International Business Machines Corporation Phase algebra for virtual clock and mode extraction in hierarchical designs
US9928323B2 (en) 2015-08-20 2018-03-27 Microsemi Solutions (U.S.), Inc. Method and system for functional verification and power analysis of clock-gated integrated circuits
US9639641B1 (en) * 2015-08-20 2017-05-02 Microsemi Storage Solutions (U.S.), Inc. Method and system for functional verification and power analysis of clock-gated integrated circuits
WO2017119123A1 (en) 2016-01-08 2017-07-13 三菱電機株式会社 Processor synthesis device, processor synthesis method, and processor synthesis program
US10585995B2 (en) * 2017-06-26 2020-03-10 International Business Machines Corporation Reducing clock power consumption of a computer processor
KR101952518B1 (en) 2017-09-12 2019-02-26 두산중공업 주식회사 Pipe hanger and support planning system, and method thereof

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6247134B1 (en) * 1999-03-31 2001-06-12 Synopsys, Inc. Method and system for pipe stage gating within an operating pipelined circuit for power savings
US6393579B1 (en) * 1999-12-21 2002-05-21 Intel Corporation Method and apparatus for saving power and improving performance in a collapsable pipeline using gated clocks
US6965991B1 (en) * 2000-05-12 2005-11-15 Pts Corporation Methods and apparatus for power control in a scalable array of processor elements
US20030070013A1 (en) * 2000-10-27 2003-04-10 Daniel Hansson Method and apparatus for reducing power consumption in a digital processor
US7035785B2 (en) * 2001-12-28 2006-04-25 Intel Corporation Mechanism for estimating and controlling di/dt-induced power supply voltage variations
US7100060B2 (en) * 2002-06-26 2006-08-29 Intel Corporation Techniques for utilization of asymmetric secondary processing resources
US7076681B2 (en) * 2002-07-02 2006-07-11 International Business Machines Corporation Processor with demand-driven clock throttling power reduction
US7065665B2 (en) * 2002-10-02 2006-06-20 International Business Machines Corporation Interlocked synchronous pipeline clock gating
US20040193846A1 (en) 2003-03-28 2004-09-30 Sprangle Eric A. Method and apparatus for utilizing multiple opportunity ports in a processor pipeline
US7076682B2 (en) * 2004-05-04 2006-07-11 International Business Machines Corp. Synchronous pipeline with normally transparent pipeline stages
US7752426B2 (en) * 2004-08-30 2010-07-06 Texas Instruments Incorporated Processes, circuits, devices, and systems for branch prediction and other processor improvements
US7653807B2 (en) * 2005-09-19 2010-01-26 Synopsys, Inc. Removing a pipeline bubble by blocking clock signal to downstream stage when downstream stage contains invalid data
US7401242B2 (en) * 2005-09-27 2008-07-15 International Business Machines Corporation Dynamic power management in a processor design
US7958483B1 (en) * 2006-12-21 2011-06-07 Nvidia Corporation Clock throttling based on activity-level signals
US7797561B1 (en) * 2006-12-21 2010-09-14 Nvidia Corporation Automatic functional block level clock-gating
US7802118B1 (en) * 2006-12-21 2010-09-21 Nvidia Corporation Functional block level clock-gating within a graphics processor
JP4388965B2 (en) * 2007-02-13 2009-12-24 富士通株式会社 Clock gating analysis program, recording medium recording the program, clock gating analysis device, and clock gating analysis method
US20080307240A1 (en) * 2007-06-08 2008-12-11 Texas Instruments Incorporated Power management electronic circuits, systems, and methods and processes of manufacture

Also Published As

Publication number Publication date
TW200915724A (en) 2009-04-01
KR20100037628A (en) 2010-04-09
WO2009024540A3 (en) 2009-09-17
DE602008006561D1 (en) 2011-06-09
JP5147944B2 (en) 2013-02-20
EP2179342A2 (en) 2010-04-28
US20090055668A1 (en) 2009-02-26
WO2009024540A2 (en) 2009-02-26
EP2179342B1 (en) 2011-04-27
CN101779179A (en) 2010-07-14
US8073669B2 (en) 2011-12-06
JP2010537293A (en) 2010-12-02
CN101779179B (en) 2012-07-11

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Legal Events

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