AT444555T - Solid phase clock and strobe-signals in chained chips - Google Patents

Solid phase clock and strobe-signals in chained chips

Info

Publication number
AT444555T
AT444555T AT04815495T AT04815495T AT444555T AT 444555 T AT444555 T AT 444555T AT 04815495 T AT04815495 T AT 04815495T AT 04815495 T AT04815495 T AT 04815495T AT 444555 T AT444555 T AT 444555T
Authority
AT
Austria
Prior art keywords
strobe
signals
solid phase
phase clock
chained
Prior art date
Application number
AT04815495T
Other languages
German (de)
Inventor
Stephen Mooney
Joseph Kennedy
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US10/749,677 priority Critical patent/US7031221B2/en
Application filed by Intel Corp filed Critical Intel Corp
Priority to PCT/US2004/043426 priority patent/WO2005066966A1/en
Publication of AT444555T publication Critical patent/AT444555T/en

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066Output synchronization
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1075Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1093Input synchronization
AT04815495T 2003-12-30 2004-12-23 Solid phase clock and strobe-signals in chained chips AT444555T (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US10/749,677 US7031221B2 (en) 2003-12-30 2003-12-30 Fixed phase clock and strobe signals in daisy chained chips
PCT/US2004/043426 WO2005066966A1 (en) 2003-12-30 2004-12-23 Fixed phase clock and strobe signals in daisy chained chips

Publications (1)

Publication Number Publication Date
AT444555T true AT444555T (en) 2009-10-15

Family

ID=34711113

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04815495T AT444555T (en) 2003-12-30 2004-12-23 Solid phase clock and strobe-signals in chained chips

Country Status (9)

Country Link
US (1) US7031221B2 (en)
EP (1) EP1700308B1 (en)
KR (1) KR100806465B1 (en)
CN (1) CN1890754B (en)
AT (1) AT444555T (en)
DE (1) DE602004023423D1 (en)
HK (1) HK1091941A1 (en)
TW (1) TWI269950B (en)
WO (1) WO2005066966A1 (en)

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US8284881B2 (en) * 2005-11-03 2012-10-09 Nxp B.V. Data interface and method of seeking synchronization
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US8433874B2 (en) * 2006-12-06 2013-04-30 Mosaid Technologies Incorporated Address assignment and type recognition of serially interconnected memory devices of mixed type
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US7554855B2 (en) * 2006-12-20 2009-06-30 Mosaid Technologies Incorporated Hybrid solid-state memory system having volatile and non-volatile memory
CN101617371B (en) 2007-02-16 2014-03-26 莫塞德技术公司 Non-volatile semiconductor memory having multiple external power supplies
US8122202B2 (en) * 2007-02-16 2012-02-21 Peter Gillingham Reduced pin count interface
US8086785B2 (en) 2007-02-22 2011-12-27 Mosaid Technologies Incorporated System and method of page buffer operation for memory devices
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KR100885915B1 (en) * 2007-02-27 2009-02-26 삼성전자주식회사 Inter-communicating multi memory chip and system including the same
US7865756B2 (en) * 2007-03-12 2011-01-04 Mosaid Technologies Incorporated Methods and apparatus for clock signal synchronization in a configuration of series-connected semiconductor devices
US7904859B2 (en) 2007-05-09 2011-03-08 Synopsys, Inc. Method and apparatus for determining a phase relationship between asynchronous clock signals
US7688652B2 (en) * 2007-07-18 2010-03-30 Mosaid Technologies Incorporated Storage of data in memory via packet strobing
WO2009062280A1 (en) * 2007-11-15 2009-05-22 Mosaid Technologies Incorporated Methods and systems for failure isolation and data recovery in a configuration of series-connected semiconductor devices
US8825939B2 (en) * 2007-12-12 2014-09-02 Conversant Intellectual Property Management Inc. Semiconductor memory device suitable for interconnection in a ring topology
US8781053B2 (en) * 2007-12-14 2014-07-15 Conversant Intellectual Property Management Incorporated Clock reproducing and timing method in a system having a plurality of devices
US8467486B2 (en) 2007-12-14 2013-06-18 Mosaid Technologies Incorporated Memory controller with flexible data alignment to clock
US8291248B2 (en) 2007-12-21 2012-10-16 Mosaid Technologies Incorporated Non-volatile semiconductor memory device with power saving feature
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US8582382B2 (en) * 2010-03-23 2013-11-12 Mosaid Technologies Incorporated Memory system having a plurality of serially connected devices
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Also Published As

Publication number Publication date
KR20060101786A (en) 2006-09-26
HK1091941A1 (en) 2010-01-22
KR100806465B1 (en) 2008-02-21
TW200525319A (en) 2005-08-01
US7031221B2 (en) 2006-04-18
EP1700308A1 (en) 2006-09-13
EP1700308B1 (en) 2009-09-30
DE602004023423D1 (en) 2009-11-12
CN1890754A (en) 2007-01-03
CN1890754B (en) 2010-05-26
WO2005066966A1 (en) 2005-07-21
TWI269950B (en) 2007-01-01
US20050146980A1 (en) 2005-07-07

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