AT432497T - System and method for adaptively optimizing the key ratio - Google Patents

System and method for adaptively optimizing the key ratio

Info

Publication number
AT432497T
AT432497T AT04756590T AT04756590T AT432497T AT 432497 T AT432497 T AT 432497T AT 04756590 T AT04756590 T AT 04756590T AT 04756590 T AT04756590 T AT 04756590T AT 432497 T AT432497 T AT 432497T
Authority
AT
Austria
Prior art keywords
system
method
key ratio
adaptively optimizing
adaptively
Prior art date
Application number
AT04756590T
Other languages
German (de)
Inventor
Huy Nguyen
Roxanne Vu
Leung Yu
Benedict Lau
Original Assignee
Rambus Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US10/661,225 priority Critical patent/US7307461B2/en
Application filed by Rambus Inc filed Critical Rambus Inc
Priority to PCT/US2004/021368 priority patent/WO2005036399A1/en
Publication of AT432497T publication Critical patent/AT432497T/en

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1093Input synchronization
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222Clock generating, synchronizing or distributing circuits within memory device
AT04756590T 2003-09-12 2004-06-29 System and method for adaptively optimizing the key ratio AT432497T (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US10/661,225 US7307461B2 (en) 2003-09-12 2003-09-12 System and method for adaptive duty cycle optimization
PCT/US2004/021368 WO2005036399A1 (en) 2003-09-12 2004-06-29 System and method for adaptive duty cycle optimization

Publications (1)

Publication Number Publication Date
AT432497T true AT432497T (en) 2009-06-15

Family

ID=34273829

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04756590T AT432497T (en) 2003-09-12 2004-06-29 System and method for adaptively optimizing the key ratio

Country Status (5)

Country Link
US (1) US7307461B2 (en)
EP (1) EP1668510B1 (en)
AT (1) AT432497T (en)
DE (1) DE602004021274D1 (en)
WO (1) WO2005036399A1 (en)

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US7307461B2 (en) 2003-09-12 2007-12-11 Rambus Inc. System and method for adaptive duty cycle optimization
US20060002493A1 (en) * 2004-06-30 2006-01-05 Infineon Technologies Ag Method and device for generating a duty cycle related output signal
US7469354B2 (en) * 2005-04-21 2008-12-23 Infineon Technologies Ag Circuit including a deskew circuit for asymmetrically delaying rising and falling edges
KR100687012B1 (en) * 2006-02-14 2007-02-20 삼성전자주식회사 Device and mehtod of frequency transformation and receiver including the same
US7489176B2 (en) * 2006-04-28 2009-02-10 Rambus Inc. Clock distribution circuit
KR100808591B1 (en) * 2006-06-30 2008-02-29 주식회사 하이닉스반도체 Clock tree circuit and duty correction test method using the same and semiconductor memory device comprising same
KR100763849B1 (en) * 2006-08-10 2007-10-05 삼성전자주식회사 Multi-phase error correction circuit, method there-of and semiconductor device including the circuit
KR100771887B1 (en) * 2006-10-17 2007-11-01 삼성전자주식회사 Duty detector and duty detection/correction circuit including the same
US7764734B2 (en) * 2006-10-31 2010-07-27 Winbond Electronics Corporation Digital pulse width modulation with variable period and error distribution
US7667512B2 (en) * 2007-03-29 2010-02-23 Standard Microsystems Corporation Duty cycle comparator
US8767696B2 (en) * 2007-07-23 2014-07-01 The Boeing Company System and method for media access control for a duty cycle network
KR100903370B1 (en) * 2007-11-02 2009-06-23 주식회사 하이닉스반도체 Data clock training circuit, semiconductor memory device and system having the same
US7821315B2 (en) * 2007-11-08 2010-10-26 Qualcomm Incorporated Adjustable duty cycle circuit
US7609583B2 (en) * 2007-11-12 2009-10-27 Micron Technology, Inc. Selective edge phase mixing
US7839194B2 (en) * 2007-11-21 2010-11-23 Rambus Inc. Clock circuitry for generating multiple clocks with time-multiplexed duty cycle adjustment
TW200926133A (en) * 2007-12-14 2009-06-16 Realtek Semiconductor Corp Display processing device and timing controller
US8615205B2 (en) 2007-12-18 2013-12-24 Qualcomm Incorporated I-Q mismatch calibration and method
US8125259B2 (en) * 2008-01-03 2012-02-28 Agere Systems Inc. Duty cycle distortion (DCD) jitter modeling, calibration and generation methods
KR20090089500A (en) * 2008-02-19 2009-08-24 주식회사 하이닉스반도체 Duty cycle correction circuit
US8970272B2 (en) 2008-05-15 2015-03-03 Qualcomm Incorporated High-speed low-power latches
US9367711B1 (en) * 2008-09-04 2016-06-14 Intelleflex Corporation Battery assisted RFID tag with square-law receiver and optional part time active behavior
JP2012504263A (en) * 2008-09-30 2012-02-16 モサイド・テクノロジーズ・インコーポレーテッド Serially connected memory system with output delay adjustment
US8181056B2 (en) 2008-09-30 2012-05-15 Mosaid Technologies Incorporated Serial-connected memory system with output delay adjustment
US8161313B2 (en) 2008-09-30 2012-04-17 Mosaid Technologies Incorporated Serial-connected memory system with duty cycle correction
US8712357B2 (en) 2008-11-13 2014-04-29 Qualcomm Incorporated LO generation with deskewed input oscillator signal
US8718574B2 (en) * 2008-11-25 2014-05-06 Qualcomm Incorporated Duty cycle adjustment for a local oscillator signal
JP5231289B2 (en) * 2009-03-02 2013-07-10 ルネサスエレクトロニクス株式会社 Duty ratio correction circuit and duty ratio correction method
KR101006088B1 (en) * 2009-06-04 2011-01-06 주식회사 하이닉스반도체 Semiconductor memory apparatus for guaranteeing reliability of data transmission and semiconductor system having the same
US8847638B2 (en) 2009-07-02 2014-09-30 Qualcomm Incorporated High speed divide-by-two circuit
US8791740B2 (en) 2009-07-16 2014-07-29 Qualcomm Incorporated Systems and methods for reducing average current consumption in a local oscillator path
KR101239709B1 (en) * 2010-10-29 2013-03-06 에스케이하이닉스 주식회사 Duty Cycle Correcting Circuit of a Semiconductor Memory Apparatus
US8854098B2 (en) 2011-01-21 2014-10-07 Qualcomm Incorporated System for I-Q phase mismatch detection and correction
US8665665B2 (en) * 2011-03-30 2014-03-04 Mediatek Inc. Apparatus and method to adjust clock duty cycle of memory
US8817914B2 (en) * 2011-08-26 2014-08-26 Nanya Technology Corporation Interactive digital duty cycle compensation circuit for receiver
US8432208B2 (en) * 2011-09-28 2013-04-30 Microchip Technology Incorporated Maintaining pulse width modulation data-set coherency
US8432207B1 (en) 2011-12-30 2013-04-30 Advanced Micro Devices, Inc. Method and apparatus for correcting the duty cycle of a high speed clock
CN104205263A (en) * 2012-01-23 2014-12-10 犹他州立大学 Dual side control for inductive power transfer
US9154077B2 (en) 2012-04-12 2015-10-06 Qualcomm Incorporated Compact high frequency divider
US9148135B2 (en) * 2012-06-26 2015-09-29 Taiwan Semiconductor Manufacturing Co., Ltd. Real time automatic and background calibration at embedded duty cycle correlation
EP2787640A1 (en) 2013-04-05 2014-10-08 Technische Universität Darmstadt A wide range programmable duty cycle corrector
JP6476659B2 (en) * 2014-08-28 2019-03-06 富士通株式会社 Signal reproduction circuit and signal reproduction method
US20190237127A1 (en) * 2018-01-31 2019-08-01 Samsung Electronics Co., Ltd. Memory device adjusting duty cycle and memory system having the same

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US4475210A (en) * 1982-02-26 1984-10-02 International Telephone And Telegraph Corporation Data eye monitor
US6125157A (en) 1997-02-06 2000-09-26 Rambus, Inc. Delay-locked loop circuitry for clock delay adjustment
JP3072833B2 (en) 1997-05-23 2000-08-07 日本電気テレコムシステム株式会社 Digital pll circuit
US6829316B1 (en) * 1998-04-28 2004-12-07 Matsushita Electric Industrial Co., Ltd. Input circuit and output circuit
US6016282A (en) 1998-05-28 2000-01-18 Micron Technology, Inc. Clock vernier adjustment
US6862296B1 (en) * 1999-12-21 2005-03-01 Lsi Logic Corporation Receive deserializer circuit for framing parallel data
EP1314249A2 (en) * 2000-09-01 2003-05-28 Honeywell International Inc. Multi-channel precision synchronous voltage-to-frequency converter
US7298807B2 (en) 2003-02-11 2007-11-20 Rambus Inc. Circuit, apparatus and method for adjusting a duty-cycle of a clock signal in response to incoming serial data
US7307461B2 (en) 2003-09-12 2007-12-11 Rambus Inc. System and method for adaptive duty cycle optimization

Also Published As

Publication number Publication date
US7307461B2 (en) 2007-12-11
US20050058233A1 (en) 2005-03-17
WO2005036399A1 (en) 2005-04-21
DE602004021274D1 (en) 2009-07-09
EP1668510B1 (en) 2009-05-27
EP1668510A1 (en) 2006-06-14

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Legal Events

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RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties