AT373876T - Improved layout of an SRAM memory cell - Google Patents

Improved layout of an SRAM memory cell

Info

Publication number
AT373876T
AT373876T AT05718464T AT05718464T AT373876T AT 373876 T AT373876 T AT 373876T AT 05718464 T AT05718464 T AT 05718464T AT 05718464 T AT05718464 T AT 05718464T AT 373876 T AT373876 T AT 373876T
Authority
AT
Austria
Prior art keywords
memory cell
sram memory
improved layout
layout
improved
Prior art date
Application number
AT05718464T
Other languages
German (de)
Inventor
Cedric Mayor
Denis Dufourt
Original Assignee
Soisic
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US55916704P priority Critical
Application filed by Soisic filed Critical Soisic
Publication of AT373876T publication Critical patent/AT373876T/en

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/11Static random access memory structures
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/11Static random access memory structures
    • H01L27/1104Static random access memory structures the load element being a MOSFET transistor
AT05718464T 2004-04-01 2005-03-25 Improved layout of an SRAM memory cell AT373876T (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US55916704P true 2004-04-01 2004-04-01

Publications (1)

Publication Number Publication Date
AT373876T true AT373876T (en) 2007-10-15

Family

ID=34964577

Family Applications (1)

Application Number Title Priority Date Filing Date
AT05718464T AT373876T (en) 2004-04-01 2005-03-25 Improved layout of an SRAM memory cell

Country Status (6)

Country Link
US (1) US7706172B2 (en)
EP (1) EP1730777B1 (en)
JP (1) JP5149617B2 (en)
AT (1) AT373876T (en)
DE (1) DE602005002546T2 (en)
WO (1) WO2005096381A1 (en)

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8653857B2 (en) 2006-03-09 2014-02-18 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US7446352B2 (en) 2006-03-09 2008-11-04 Tela Innovations, Inc. Dynamic array architecture
US8448102B2 (en) 2006-03-09 2013-05-21 Tela Innovations, Inc. Optimizing layout of irregular structures in regular layout context
US9230910B2 (en) 2006-03-09 2016-01-05 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US8658542B2 (en) 2006-03-09 2014-02-25 Tela Innovations, Inc. Coarse grid design methods and structures
US9009641B2 (en) 2006-03-09 2015-04-14 Tela Innovations, Inc. Circuits with linear finfet structures
US9035359B2 (en) 2006-03-09 2015-05-19 Tela Innovations, Inc. Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods
US8839175B2 (en) 2006-03-09 2014-09-16 Tela Innovations, Inc. Scalable meta-data objects
US8667443B2 (en) 2007-03-05 2014-03-04 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
SG10201608214SA (en) 2008-07-16 2016-11-29 Tela Innovations Inc Methods for cell phasing and placement in dynamic array architecture and implementation of the same
US7908578B2 (en) 2007-08-02 2011-03-15 Tela Innovations, Inc. Methods for designing semiconductor device with dynamic array section
US7763534B2 (en) 2007-10-26 2010-07-27 Tela Innovations, Inc. Methods, structures and designs for self-aligning local interconnects used in integrated circuits
US8541879B2 (en) 2007-12-13 2013-09-24 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US8453094B2 (en) 2008-01-31 2013-05-28 Tela Innovations, Inc. Enforcement of semiconductor structure regularity for localized transistors and interconnect
US7956421B2 (en) 2008-03-13 2011-06-07 Tela Innovations, Inc. Cross-coupled transistor layouts in restricted gate level layout architecture
US7939443B2 (en) 2008-03-27 2011-05-10 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same
US9122832B2 (en) 2008-08-01 2015-09-01 Tela Innovations, Inc. Methods for controlling microloading variation in semiconductor wafer layout and fabrication
JP5364108B2 (en) * 2009-01-19 2013-12-11 株式会社日立製作所 A method of manufacturing a semiconductor device
SG165252A1 (en) 2009-03-25 2010-10-28 Unisantis Electronics Jp Ltd Semiconductor device and production method therefor
US9563733B2 (en) 2009-05-06 2017-02-07 Tela Innovations, Inc. Cell circuit and layout with linear finfet structures
JP5032532B2 (en) * 2009-06-05 2012-09-26 ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. Semiconductor device and manufacturing method thereof
JP5006378B2 (en) 2009-08-11 2012-08-22 ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. Semiconductor device and manufacturing method thereof
JP5006379B2 (en) * 2009-09-16 2012-08-22 ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. Semiconductor device
US8661392B2 (en) 2009-10-13 2014-02-25 Tela Innovations, Inc. Methods for cell boundary encroachment and layouts implementing the Same
FR2956516B1 (en) * 2010-02-15 2012-12-07 St Microelectronics Sa SRAM memory cell random ten transistors
KR101669244B1 (en) * 2010-06-08 2016-10-25 삼성전자주식회사 Sram devices and methods for fabricating the same
US9159627B2 (en) 2010-11-12 2015-10-13 Tela Innovations, Inc. Methods for linewidth modification and apparatus implementing the same
US20120120703A1 (en) * 2010-11-15 2012-05-17 Taiwan Semiconductor Manufacturing Co., Ltd. Memory device with asymmetrical bit cell arrays and balanced resistance and capacitance
US8582389B2 (en) * 2011-06-15 2013-11-12 Arm Limited Write assist in a dual write line semiconductor memory
US8717798B2 (en) * 2011-09-23 2014-05-06 Taiwan Semiconductor Manufacturing Co., Ltd. Layout for semiconductor memories
JP6034764B2 (en) * 2013-08-05 2016-11-30 ルネサスエレクトロニクス株式会社 A semiconductor memory device

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3779734B2 (en) * 1993-02-19 2006-05-31 株式会社ルネサステクノロジ The semiconductor integrated circuit device and manufacturing method thereof
US5754468A (en) * 1996-06-26 1998-05-19 Simon Fraser University Compact multiport static random access memory cell
JP3523762B2 (en) * 1996-12-19 2004-04-26 株式会社東芝 A semiconductor memory device
JP3036588B2 (en) * 1997-02-03 2000-04-24 日本電気株式会社 A semiconductor memory device
JPH1145949A (en) * 1997-07-28 1999-02-16 Mitsubishi Electric Corp Static semiconductor memory device and its manufacture
US6026012A (en) * 1998-12-30 2000-02-15 United Microelectronic Corp. Dual port random access memory
JP3526553B2 (en) * 2001-01-26 2004-05-17 松下電器産業株式会社 Sram equipment
JP4623885B2 (en) * 2001-08-16 2011-02-02 ルネサスエレクトロニクス株式会社 A semiconductor memory device
US6670642B2 (en) * 2002-01-22 2003-12-30 Renesas Technology Corporation. Semiconductor memory device using vertical-channel transistors
FR2843481B1 (en) * 2002-08-08 2005-09-16 Soisic Memory on the substrate of the silicon on insulator type
KR100450683B1 (en) * 2002-09-04 2004-10-01 삼성전자주식회사 SRAM device formed on SOI substrate
JP4005468B2 (en) * 2002-09-30 2007-11-07 富士通株式会社 Placement method and a semiconductor memory device of the memory cell
US6778462B1 (en) * 2003-05-08 2004-08-17 Lsi Logic Corporation Metal-programmable single-port SRAM array for dual-port functionality
US7345909B2 (en) * 2003-09-24 2008-03-18 Yen-Jen Chang Low-power SRAM memory cell
US7023056B2 (en) * 2003-11-26 2006-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Memory cell structure
JP2005175415A (en) * 2003-12-05 2005-06-30 Taiwan Semiconductor Manufacturing Co Ltd Integrated circuit device and its manufacturing method

Also Published As

Publication number Publication date
DE602005002546D1 (en) 2007-10-31
JP2007533122A (en) 2007-11-15
WO2005096381A1 (en) 2005-10-13
EP1730777B1 (en) 2007-09-19
US20080062756A1 (en) 2008-03-13
US7706172B2 (en) 2010-04-27
JP5149617B2 (en) 2013-02-20
DE602005002546T2 (en) 2008-06-12
EP1730777A1 (en) 2006-12-13

Similar Documents

Publication Publication Date Title
AT518856T (en) manufacturing
DE602006019839D1 (en) Global page türschloss
AT456397T (en) honeycomb structure
DE60332644D1 (en) Substrate storage tank
DE602005021577D1 (en) Fire-proof battery case
DE60319406D1 (en) Meso-substituted porphyrins
DE602005024050D1 (en) Insulation materials for solar cells
AT529896T (en) Encapsulation for solar cells
AT487362T (en) Data center-cooling
AT430384T (en) Anhydrous electrochemical cells
DE60130586D1 (en) memory cell
DE60318506D1 (en) storage structure
IS8578A (en) 3- carbamoyl - 2- pyridone derivatives
NO20051183D0 (en) Sound-proof structures
AT410585T (en) Water flooding
DE602006000126D1 (en) battery module
AT490567T (en) Microfluidic electrochemical reactors
DE602006017017D1 (en) battery module
DE60212661D1 (en) Background execution of an operation with memory cells
AT407967T (en) nucleating
NO20044141D0 (en) Electrochemical fuel cells
NO20040706L (en) Power Generation System
DE602006011246D1 (en) battery module
DE602005007722D1 (en) Multiple access points
DE602004007343D1 (en) Fuel cell vehicle

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties