AT363098T - A method for debugging reconfigurable architectures - Google Patents

A method for debugging reconfigurable architectures

Info

Publication number
AT363098T
AT363098T AT02772041T AT02772041T AT363098T AT 363098 T AT363098 T AT 363098T AT 02772041 T AT02772041 T AT 02772041T AT 02772041 T AT02772041 T AT 02772041T AT 363098 T AT363098 T AT 363098T
Authority
AT
Austria
Prior art keywords
method
reconfigurable architectures
debugging
debugging reconfigurable
architectures
Prior art date
Application number
AT02772041T
Other languages
German (de)
Inventor
Martin Vorbach
Original Assignee
Pact Xpp Technologies Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to DE10142904 priority Critical
Priority to DE10142894 priority
Priority to DE10144733 priority
Priority to DE10145795 priority
Priority to US09/967,497 priority patent/US7266725B2/en
Priority to DE10154259 priority
Priority to DE10202044 priority
Priority to DE10202175 priority
Priority to DE10206856 priority
Priority to DE10207226 priority
Priority to DE10240022 priority
Application filed by Pact Xpp Technologies Ag filed Critical Pact Xpp Technologies Ag
Publication of AT363098T publication Critical patent/AT363098T/en

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/22Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26Functional testing
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/22Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26Functional testing
    • G06F11/267Reconfiguring circuits for testing, e.g. LSSD, partitioning
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/36Preventing errors by testing or debugging software
    • G06F11/362Software debugging
    • G06F11/3648Software debugging using additional hardware
    • G06F11/3656Software debugging using additional hardware using a specific debug interface
AT02772041T 2001-09-03 2002-09-03 A method for debugging reconfigurable architectures AT363098T (en)

Priority Applications (11)

Application Number Priority Date Filing Date Title
DE10142904 2001-09-03
DE10142894 2001-09-03
DE10144733 2001-09-11
DE10145795 2001-09-17
US09/967,497 US7266725B2 (en) 2001-09-03 2001-09-28 Method for debugging reconfigurable architectures
DE10154259 2001-11-05
DE10202044 2002-01-19
DE10202175 2002-01-20
DE10206856 2002-02-18
DE10207226 2002-02-21
DE10240022 2002-08-27

Publications (1)

Publication Number Publication Date
AT363098T true AT363098T (en) 2007-06-15

Family

ID=45871926

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02772041T AT363098T (en) 2001-09-03 2002-09-03 A method for debugging reconfigurable architectures

Country Status (4)

Country Link
EP (1) EP1449083B1 (en)
AT (1) AT363098T (en)
AU (1) AU2002336896A1 (en)
WO (1) WO2003023616A2 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6542998B1 (en) 1997-02-08 2003-04-01 Pact Gmbh Method of self-synchronization of configurable elements of a programmable module
US9037807B2 (en) 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
US8058899B2 (en) 2000-10-06 2011-11-15 Martin Vorbach Logic cell array and bus system
US7444531B2 (en) 2001-03-05 2008-10-28 Pact Xpp Technologies Ag Methods and devices for treating and processing data
US7996827B2 (en) 2001-08-16 2011-08-09 Martin Vorbach Method for the translation of programs for reconfigurable architectures
US8914590B2 (en) 2002-08-07 2014-12-16 Pact Xpp Technologies Ag Data processing method and device
EP2043000B1 (en) 2002-02-18 2011-12-21 Richter, Thomas Bus systems and reconfiguration method

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5425036A (en) * 1992-09-18 1995-06-13 Quickturn Design Systems, Inc. Method and apparatus for debugging reconfigurable emulation systems
US5680583A (en) * 1994-02-16 1997-10-21 Arkos Design, Inc. Method and apparatus for a trace buffer in an emulation system
US5754827A (en) * 1995-10-13 1998-05-19 Mentor Graphics Corporation Method and apparatus for performing fully visible tracing of an emulation

Also Published As

Publication number Publication date
EP1449083A2 (en) 2004-08-25
WO2003023616A3 (en) 2003-12-18
AU2002336896A1 (en) 2003-03-24
EP1449083B1 (en) 2007-05-23
WO2003023616A2 (en) 2003-03-20
WO2003023616A8 (en) 2003-08-21

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Legal Events

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