AT320129T - Flit-cache in a packet-switching router - Google Patents

Flit-cache in a packet-switching router

Info

Publication number
AT320129T
AT320129T AT00935995T AT00935995T AT320129T AT 320129 T AT320129 T AT 320129T AT 00935995 T AT00935995 T AT 00935995T AT 00935995 T AT00935995 T AT 00935995T AT 320129 T AT320129 T AT 320129T
Authority
AT
Austria
Prior art keywords
flit
cache
packet
switching router
router
Prior art date
Application number
AT00935995T
Other languages
German (de)
Inventor
William J Dally
Philip P Carvey
P Allen King
William F Mann
Larry R Dennison
Original Assignee
Avici Systems
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US31669999A priority Critical
Application filed by Avici Systems filed Critical Avici Systems
Publication of AT320129T publication Critical patent/AT320129T/en

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/90Queuing arrangements
    • H04L49/9063Intermediate storage in different physical parts of a node or terminal
    • H04L49/9078Intermediate storage in different physical parts of a node or terminal using an external memory or storage device
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/90Queuing arrangements
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/90Queuing arrangements
    • H04L49/901Storage descriptor, e.g. read or write pointers
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/90Queuing arrangements
    • H04L49/9047Buffer pool
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/90Queuing arrangements
    • H04L49/9063Intermediate storage in different physical parts of a node or terminal
    • H04L49/9068Intermediate storage in different physical parts of a node or terminal in the network interface card
    • H04L49/9073Early interruption upon arrival of a fraction of a packet
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/15Interconnection of switching modules
    • H04L49/1515Non-blocking multistage, e.g. Clos
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/25Routing or path finding through a switch fabric
    • H04L49/251Cut-through or wormhole routing
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/30Peripheral units, e.g. input or output ports
    • H04L49/3036Shared queuing
AT00935995T 1999-05-21 2000-05-16 Flit-cache in a packet-switching router AT320129T (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US31669999A true 1999-05-21 1999-05-21

Publications (1)

Publication Number Publication Date
AT320129T true AT320129T (en) 2006-03-15

Family

ID=23230259

Family Applications (1)

Application Number Title Priority Date Filing Date
AT00935995T AT320129T (en) 1999-05-21 2000-05-16 Flit-cache in a packet-switching router

Country Status (9)

Country Link
US (1) US20050018609A1 (en)
EP (1) EP1183828B1 (en)
JP (1) JP2003512746A (en)
CN (1) CN1351791A (en)
AT (1) AT320129T (en)
AU (1) AU5137000A (en)
CA (1) CA2372644A1 (en)
DE (1) DE60026518T2 (en)
WO (1) WO2000072530A2 (en)

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US7720095B2 (en) 2003-08-27 2010-05-18 Fortinet, Inc. Heterogeneous media packet bridging
US7411969B2 (en) * 2003-10-28 2008-08-12 Intel Corporation Method, system, and apparatus for a credit based flow control in a computer system
US7406080B2 (en) * 2004-06-15 2008-07-29 International Business Machines Corporation Method and structure for enqueuing data packets for processing
US7719964B2 (en) * 2004-08-12 2010-05-18 Eric Morton Data credit pooling for point-to-point links
US7518996B2 (en) * 2004-09-16 2009-04-14 Jinsalas Solutions, Llc Fast credit system
US7698744B2 (en) 2004-12-03 2010-04-13 Whitecell Software Inc. Secure system for allowing the execution of authorized computer program code
US7602777B2 (en) * 2004-12-17 2009-10-13 Michael Ho Cascaded connection matrices in a distributed cross-connection system
US7849441B2 (en) * 2005-06-27 2010-12-07 Ikoa Corporation Method for specifying stateful, transaction-oriented systems for flexible mapping to structurally configurable, in-memory processing semiconductor device
US8325768B2 (en) 2005-08-24 2012-12-04 Intel Corporation Interleaving data packets in a packet-based communication system
US7864792B2 (en) * 2007-04-20 2011-01-04 Cray, Inc. Load balancing for communications within a multiprocessor computer system
US7783823B2 (en) * 2007-07-31 2010-08-24 Hewlett-Packard Development Company, L.P. Hardware device data buffer
US7836198B2 (en) * 2008-03-20 2010-11-16 International Business Machines Corporation Ethernet virtualization using hardware control flow override
US8539130B2 (en) * 2009-09-24 2013-09-17 Nvidia Corporation Virtual channels for effective packet transfer
US8571050B1 (en) * 2010-06-18 2013-10-29 Integrated Device Technology, Inc. Method and apparatus to optimize class of service under multiple VCs with mixed reliable transfer and continuous transfer modes
US9253248B2 (en) * 2010-11-15 2016-02-02 Interactic Holdings, Llc Parallel information system utilizing flow control and virtual channels
KR20170072645A (en) 2015-12-17 2017-06-27 삼성전자주식회사 Processor and method for processing data thereof

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Also Published As

Publication number Publication date
DE60026518T2 (en) 2006-11-16
WO2000072530A3 (en) 2001-02-08
CN1351791A (en) 2002-05-29
AU5137000A (en) 2000-12-12
EP1183828A2 (en) 2002-03-06
DE60026518D1 (en) 2006-05-04
CA2372644A1 (en) 2000-11-30
WO2000072530A2 (en) 2000-11-30
EP1183828B1 (en) 2006-03-08
US20050018609A1 (en) 2005-01-27
JP2003512746A (en) 2003-04-02

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Legal Events

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RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties