AT243390T - A method for automatic dynamic reloading of data flow processors (dfps) and modules having a two- or multi-dimensional programmable cell structure (FPGAs DPGAs, or the like.) - Google Patents

A method for automatic dynamic reloading of data flow processors (dfps) and modules having a two- or multi-dimensional programmable cell structure (FPGAs DPGAs, or the like.)

Info

Publication number
AT243390T
AT243390T AT97954332T AT97954332T AT243390T AT 243390 T AT243390 T AT 243390T AT 97954332 T AT97954332 T AT 97954332T AT 97954332 T AT97954332 T AT 97954332T AT 243390 T AT243390 T AT 243390T
Authority
AT
Austria
Prior art keywords
dpgas
dfps
fpgas
modules
multi
Prior art date
Application number
AT97954332T
Other languages
German (de)
Inventor
Martin Vorbach
Robert Muench
Original Assignee
Pact Inf Tech Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to DE1996154846 priority Critical patent/DE19654846A1/en
Application filed by Pact Inf Tech Gmbh filed Critical Pact Inf Tech Gmbh
Priority to PCT/DE1997/002998 priority patent/WO1998029952A1/en
Publication of AT243390T publication Critical patent/AT243390T/en

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored program computers
    • G06F15/78Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748Structural details of configuration resources
    • H03K19/17752Structural details of configuration resources for hot reconfiguration
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748Structural details of configuration resources
    • H03K19/17756Structural details of configuration resources for partial configuration or reconfiguration
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748Structural details of configuration resources
    • H03K19/1776Structural details of configuration resources for memories
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748Structural details of configuration resources
    • H03K19/17776Structural details of configuration resources for speeding up configuration or reconfiguration
AT97954332T 1996-12-27 1997-12-22 A method for automatic dynamic reloading of data flow processors (dfps) and modules having a two- or multi-dimensional programmable cell structure (FPGAs DPGAs, or the like.) AT243390T (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
DE1996154846 DE19654846A1 (en) 1996-12-27 1996-12-27 A method for automatic dynamic reloading of Datenflußprozessoren (DFP) and modules having a two- or multi-dimensional programmable cell structure (FPGAs, DPGAs, o. The like).
PCT/DE1997/002998 WO1998029952A1 (en) 1996-12-27 1997-12-22 METHOD FOR AUTOMATIC DYNAMIC UNLOADING OF DATA FLOW PROCESSORS (DFP) AS WELL AS MODULES WITH BIDIMENSIONAL OR MULTIDIMENSIONAL PROGRAMMABLE CELL STRUCTURES (EPGAs, DPGAs OR THE LIKE)

Publications (1)

Publication Number Publication Date
AT243390T true AT243390T (en) 2003-07-15

Family

ID=7816473

Family Applications (1)

Application Number Title Priority Date Filing Date
AT97954332T AT243390T (en) 1996-12-27 1997-12-22 A method for automatic dynamic reloading of data flow processors (dfps) and modules having a two- or multi-dimensional programmable cell structure (FPGAs DPGAs, or the like.)

Country Status (4)

Country Link
US (2) US7822881B2 (en)
EP (1) EP1329816B1 (en)
JP (2) JP3961028B2 (en)
AT (1) AT243390T (en)

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US6542998B1 (en) 1997-02-08 2003-04-01 Pact Gmbh Method of self-synchronization of configurable elements of a programmable module
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US8914590B2 (en) 2002-08-07 2014-12-16 Pact Xpp Technologies Ag Data processing method and device
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