AT204996T - Shock-operation sram to use for a high-speed clock - Google Patents

Shock-operation sram to use for a high-speed clock

Info

Publication number
AT204996T
AT204996T AT94301988T AT94301988T AT204996T AT 204996 T AT204996 T AT 204996T AT 94301988 T AT94301988 T AT 94301988T AT 94301988 T AT94301988 T AT 94301988T AT 204996 T AT204996 T AT 204996T
Authority
AT
Austria
Prior art keywords
shock
high
use
speed clock
sram
Prior art date
Application number
AT94301988T
Other languages
German (de)
Inventor
Gary W Thome
Michael J Collins
Original Assignee
Compaq Computer Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US08/034,288 priority Critical patent/US5604884A/en
Application filed by Compaq Computer Corp filed Critical Compaq Computer Corp
Publication of AT204996T publication Critical patent/AT204996T/en

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/18Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
AT94301988T 1993-03-22 1994-03-21 Shock-operation sram to use for a high-speed clock AT204996T (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US08/034,288 US5604884A (en) 1993-03-22 1993-03-22 Burst SRAMS for use with a high speed clock

Publications (1)

Publication Number Publication Date
AT204996T true AT204996T (en) 2001-09-15

Family

ID=21875467

Family Applications (1)

Application Number Title Priority Date Filing Date
AT94301988T AT204996T (en) 1993-03-22 1994-03-21 Shock-operation sram to use for a high-speed clock

Country Status (5)

Country Link
US (2) US5604884A (en)
EP (1) EP0621539B1 (en)
AT (1) AT204996T (en)
CA (1) CA2119200C (en)
DE (2) DE69428071T2 (en)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6094703A (en) 1995-02-21 2000-07-25 Micron Technology, Inc. Synchronous SRAM having pipelined memory access enable for a burst of addresses
US6205514B1 (en) 1995-02-21 2001-03-20 Micron Technology, Inc. Synchronous SRAM having global write enable
US5848431A (en) * 1995-02-21 1998-12-08 Micron Technology, Inc. Synchronous SRAMs having multiple chip select inputs and a standby chip enable input
US5745913A (en) * 1996-08-05 1998-04-28 Exponential Technology, Inc. Multi-processor DRAM controller that prioritizes row-miss requests to stale banks
US6631454B1 (en) * 1996-11-13 2003-10-07 Intel Corporation Processor and data cache with data storage unit and tag hit/miss logic operated at a first and second clock frequencies
US5818794A (en) * 1997-05-16 1998-10-06 Intel Corporation Internally controlled signal system for controlling the operation of a device
US6044432A (en) * 1997-11-12 2000-03-28 Vlsi Technology, Inc. Method and system for latching an address for accessing synchronous random access memory using a single address status signal control line
US6192459B1 (en) 1998-03-23 2001-02-20 Intel Corporation Method and apparatus for retrieving data from a data storage device
US6621761B2 (en) * 2000-05-31 2003-09-16 Advanced Micro Devices, Inc. Burst architecture for a flash memory
US7124281B1 (en) * 2000-09-21 2006-10-17 Freescale Semiconductor, Inc. Processing system having sequential address indicator signals
US6904505B1 (en) 2000-10-12 2005-06-07 Emulex Design & Manufacturing Corporation Method for determining valid bytes for multiple-byte burst memories
US7072347B2 (en) * 2001-02-23 2006-07-04 International Business Machines Corporation Assignment of packet descriptor field positions in a network processor
DE10255685B3 (en) 2002-11-28 2004-07-29 Infineon Technologies Ag Clock synchronization circuit
US7383388B2 (en) 2004-06-17 2008-06-03 International Business Machines Corporation Method for storing data
US7430642B2 (en) * 2005-06-10 2008-09-30 Freescale Semiconductor, Inc. System and method for unified cache access using sequential instruction information
EP2323009A1 (en) * 2009-11-13 2011-05-18 SiTel Semiconductor B.V. Electronic device with reduced power consumption in external memory

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4631659A (en) * 1984-03-08 1986-12-23 Texas Instruments Incorporated Memory interface with automatic delay state
US4618947B1 (en) * 1984-07-26 1998-01-06 Texas Instruments Inc Dynamic memory with improved address counter for serial modes
US5134699A (en) * 1988-06-24 1992-07-28 Advanced Micro Devices, Inc. Programmable burst data transfer apparatus and technique
US5239639A (en) * 1990-11-09 1993-08-24 Intel Corporation Efficient memory controller with an independent clock
US5210845A (en) * 1990-11-28 1993-05-11 Intel Corporation Controller for two-way set associative cache
JP3992757B2 (en) * 1991-04-23 2007-10-17 テキサス インスツルメンツ インコーポレイテツド A system that includes a memory synchronized with a microprocessor, and a data processor, a synchronous memory, a peripheral device and a system clock

Also Published As

Publication number Publication date
DE69428071T2 (en) 2002-04-25
CA2119200C (en) 1999-01-19
EP0621539A1 (en) 1994-10-26
EP0621539B1 (en) 2001-08-29
US5604884A (en) 1997-02-18
US5809549A (en) 1998-09-15
DE69428071D1 (en) 2001-10-04
CA2119200A1 (en) 1994-09-23

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