AT162897T - Method and device for the acceleration of branch instructions - Google Patents

Method and device for the acceleration of branch instructions

Info

Publication number
AT162897T
AT162897T AT90305401T AT90305401T AT162897T AT 162897 T AT162897 T AT 162897T AT 90305401 T AT90305401 T AT 90305401T AT 90305401 T AT90305401 T AT 90305401T AT 162897 T AT162897 T AT 162897T
Authority
AT
Austria
Prior art keywords
acceleration
device
method
branch instructions
branch
Prior art date
Application number
AT90305401T
Other languages
German (de)
Inventor
William Michael Johnson
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US07/361,870 priority Critical patent/US5136697A/en
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of AT162897T publication Critical patent/AT162897T/en

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802Instruction prefetching
    • G06F9/3804Instruction prefetching for branches, e.g. hedging, branch folding
    • G06F9/3806Instruction prefetching for branches, e.g. hedging, branch folding using address prediction, e.g. return stack, branch history buffer
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling, out of order instruction execution
AT90305401T 1989-06-06 1990-05-18 Method and device for the acceleration of branch instructions AT162897T (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US07/361,870 US5136697A (en) 1989-06-06 1989-06-06 System for reducing delay for execution subsequent to correctly predicted branch instruction using fetch information stored with each block of instructions in cache

Publications (1)

Publication Number Publication Date
AT162897T true AT162897T (en) 1998-02-15

Family

ID=23423749

Family Applications (1)

Application Number Title Priority Date Filing Date
AT90305401T AT162897T (en) 1989-06-06 1990-05-18 Method and device for the acceleration of branch instructions

Country Status (6)

Country Link
US (2) US5136697A (en)
EP (1) EP0401992B1 (en)
JP (1) JP2889955B2 (en)
AT (1) AT162897T (en)
DE (2) DE69031991D1 (en)
ES (1) ES2111528T3 (en)

Families Citing this family (220)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0795271B2 (en) * 1989-06-20 1995-10-11 富士通株式会社 A branch instruction execution unit
US5163140A (en) * 1990-02-26 1992-11-10 Nexgen Microsystems Two-level branch prediction cache
US5226130A (en) * 1990-02-26 1993-07-06 Nexgen Microsystems Method and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency
US5230068A (en) * 1990-02-26 1993-07-20 Nexgen Microsystems Cache memory system for dynamically altering single cache memory line as either branch target entry or pre-fetch instruction queue based upon instruction sequence
US5317718A (en) * 1990-03-27 1994-05-31 Digital Equipment Corporation Data processing system and method with prefetch buffers
CA2045791A1 (en) * 1990-06-29 1991-12-30 Richard Lee Sites Branch performance in high speed processor
US5530941A (en) * 1990-08-06 1996-06-25 Ncr Corporation System and method for prefetching data from a main computer memory into a cache memory
WO1992006426A1 (en) * 1990-10-09 1992-04-16 Nexgen Microsystems Method and apparatus for parallel decoding of instructions with branch prediction look-up
JP2532300B2 (en) * 1990-10-17 1996-09-11 三菱電機株式会社 Instruction supply device in a parallel processor
JP2535252B2 (en) * 1990-10-17 1996-09-18 三菱電機株式会社 Parallel processor
US5446849A (en) * 1990-11-30 1995-08-29 Kabushiki Kaisha Toshiba Electronic computer which executes squash branching
US5265213A (en) * 1990-12-10 1993-11-23 Intel Corporation Pipeline system for executing predicted branch target instruction in a cycle concurrently with the execution of branch instruction
DE4211222B4 (en) * 1991-04-05 2009-05-28 Kabushiki Kaisha Toshiba, Kawasaki A branch predictor and branch prediction method for a super scalar processor
US5454089A (en) * 1991-04-17 1995-09-26 Intel Corporation Branch look ahead adder for use in an instruction pipeline sequencer with multiple instruction decoding
US5630157A (en) * 1991-06-13 1997-05-13 International Business Machines Corporation Computer organization for multiple and out-of-order execution of condition code testing and setting instructions
US5539911A (en) * 1991-07-08 1996-07-23 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US5493687A (en) 1991-07-08 1996-02-20 Seiko Epson Corporation RISC microprocessor architecture implementing multiple typed register sets
JP3441071B2 (en) 1991-07-08 2003-08-25 セイコーエプソン株式会社 Microprocessor and the data processing device
JP2875909B2 (en) * 1991-07-12 1999-03-31 三菱電機株式会社 Parallel processor
JP2773471B2 (en) * 1991-07-24 1998-07-09 日本電気株式会社 The information processing apparatus
US5649097A (en) * 1991-10-25 1997-07-15 International Business Machines Corporation Synchronizing a prediction RAM
JPH07506921A (en) * 1992-03-06 1995-07-27
KR957001101A (en) 1992-03-31 1995-02-20 요시오 야마자끼 Superscalar out yieseu Mr. (risc) instruction scheduling
JP3575617B2 (en) * 1992-04-29 2004-10-13 サン・マイクロシステムズ・インコーポレイテッドSun Microsystems, Inc. Computer system
DE69308548T2 (en) 1992-05-01 1997-06-12 Seiko Epson Corp Device and method for command statements in a superscalar processor.
EP0583089B1 (en) * 1992-08-12 2000-01-26 Advanced Micro Devices, Inc. Instruction decoder
EP0586057B1 (en) * 1992-08-31 2000-03-01 Sun Microsystems, Inc. Rapid instruction (pre)fetching and dispatching using prior (pre)fetch predictive annotations
US5337415A (en) * 1992-12-04 1994-08-09 Hewlett-Packard Company Predecoding instructions for supercalar dependency indicating simultaneous execution for increased operating frequency
US5628021A (en) 1992-12-31 1997-05-06 Seiko Epson Corporation System and method for assigning tags to control instruction processing in a superscalar processor
DE69320991T2 (en) 1992-12-31 1999-01-28 Seiko Epson Corp System and method for changing the names of registers
US5467473A (en) * 1993-01-08 1995-11-14 International Business Machines Corporation Out of order instruction load and store comparison
US5898882A (en) * 1993-01-08 1999-04-27 International Business Machines Corporation Method and system for enhanced instruction dispatch in a superscalar processor system utilizing independently accessed intermediate storage
US5367703A (en) * 1993-01-08 1994-11-22 International Business Machines Corporation Method and system for enhanced branch history prediction accuracy in a superscalar processor system
US5696958A (en) * 1993-01-11 1997-12-09 Silicon Graphics, Inc. Method and apparatus for reducing delays following the execution of a branch instruction in an instruction pipeline
US5537573A (en) * 1993-05-28 1996-07-16 Rambus, Inc. Cache system and method for prefetching of data
US5826069A (en) * 1993-09-27 1998-10-20 Intel Corporation Having write merge and data override capability for a superscalar processing device
US5826094A (en) * 1993-09-30 1998-10-20 Intel Corporation Register alias table update to indicate architecturally visible state
US5740393A (en) * 1993-10-15 1998-04-14 Intel Corporation Instruction pointer limits in processor that performs speculative out-of-order instruction execution
US5748976A (en) * 1993-10-18 1998-05-05 Amdahl Corporation Mechanism for maintaining data coherency in a branch history instruction cache
DE69429061D1 (en) * 1993-10-29 2001-12-20 Advanced Micro Devices Inc Superskalarmikroprozessoren
DE69427734D1 (en) * 1993-10-29 2001-08-23 Advanced Micro Devices Inc Linear Addressed microprocessor cache
US5878245A (en) 1993-10-29 1999-03-02 Advanced Micro Devices, Inc. High performance load/store functional unit and data cache
US5689672A (en) * 1993-10-29 1997-11-18 Advanced Micro Devices, Inc. Pre-decoded instruction cache and method therefor particularly suitable for variable byte-length instructions
US5630082A (en) * 1993-10-29 1997-05-13 Advanced Micro Devices, Inc. Apparatus and method for instruction queue scanning
EP0651324B1 (en) * 1993-10-29 2006-03-22 Advanced Micro Devices Inc. Speculative instruction queue for variable byte length instructions
US5574928A (en) * 1993-10-29 1996-11-12 Advanced Micro Devices, Inc. Mixed integer/floating point processor core for a superscalar microprocessor with a plurality of operand buses for transferring operand segments
EP0651320B1 (en) * 1993-10-29 2001-05-23 Advanced Micro Devices Inc. Superscalar instruction decoder
US5500943A (en) * 1993-11-02 1996-03-19 Motorola, Inc. Data processor with rename buffer and FIFO buffer for in-order instruction completion
US6128721A (en) * 1993-11-17 2000-10-03 Sun Microsystems, Inc. Temporary pipeline register file for a superpipelined superscalar processor
US6079014A (en) * 1993-12-02 2000-06-20 Intel Corporation Processor that redirects an instruction fetch pipeline immediately upon detection of a mispredicted branch while committing prior instructions to an architectural state
US5604909A (en) 1993-12-15 1997-02-18 Silicon Graphics Computer Systems, Inc. Apparatus for processing instructions in a computing system
IE940855A1 (en) * 1993-12-20 1995-06-28 Motorola Inc Data processor with speculative instruction fetching and¹method of operation
US5517651A (en) * 1993-12-29 1996-05-14 Intel Corporation Method and apparatus for loading a segment register in a microprocessor capable of operating in multiple modes
US6393550B1 (en) * 1993-12-30 2002-05-21 Intel Corporation Method and apparatus for pipeline streamlining where resources are immediate or certainly retired
US6101597A (en) * 1993-12-30 2000-08-08 Intel Corporation Method and apparatus for maximum throughput scheduling of dependent operations in a pipelined processor
US5721857A (en) * 1993-12-30 1998-02-24 Intel Corporation Method and apparatus for saving the effective address of floating point memory operations in an out-of-order microprocessor
US5680565A (en) * 1993-12-30 1997-10-21 Intel Corporation Method and apparatus for performing page table walks in a microprocessor capable of processing speculative instructions
TW253946B (en) * 1994-02-04 1995-08-11 Ibm Data processor with branch prediction and method of operation
US5553256A (en) * 1994-02-28 1996-09-03 Intel Corporation Apparatus for pipeline streamlining where resources are immediate or certainly retired
US5687338A (en) * 1994-03-01 1997-11-11 Intel Corporation Method and apparatus for maintaining a macro instruction for refetching in a pipelined processor
US5559976A (en) * 1994-03-31 1996-09-24 International Business Machines Corporation System for instruction completion independent of result write-back responsive to both exception free completion of execution and completion of all logically prior instructions
US5546599A (en) * 1994-03-31 1996-08-13 International Business Machines Corporation Processing system and method of operation for processing dispatched instructions with detected exceptions
TW260765B (en) * 1994-03-31 1995-10-21 Ibm
TW353732B (en) * 1994-03-31 1999-03-01 Ibm Processing system and method of operation
JPH07281893A (en) * 1994-04-15 1995-10-27 Internatl Business Mach Corp <Ibm> Processing system and arithmetic method
US5644779A (en) * 1994-04-15 1997-07-01 International Business Machines Corporation Processing system and method of operation for concurrent processing of branch instructions with cancelling of processing of a branch instruction
US5689693A (en) * 1994-04-26 1997-11-18 Advanced Micro Devices, Inc. Range finding circuit for selecting a consecutive sequence of reorder buffer entries using circular carry lookahead
US5590352A (en) * 1994-04-26 1996-12-31 Advanced Micro Devices, Inc. Dependency checking and forwarding of variable width operands
US5632023A (en) * 1994-06-01 1997-05-20 Advanced Micro Devices, Inc. Superscalar microprocessor including flag operand renaming and forwarding apparatus
US5649225A (en) * 1994-06-01 1997-07-15 Advanced Micro Devices, Inc. Resynchronization of a superscalar processor
US5559975A (en) * 1994-06-01 1996-09-24 Advanced Micro Devices, Inc. Program counter update mechanism
US5696955A (en) * 1994-06-01 1997-12-09 Advanced Micro Devices, Inc. Floating point stack and exchange instruction
US5561782A (en) * 1994-06-30 1996-10-01 Intel Corporation Pipelined cache system having low effective latency for nonsequential accesses
US5535346A (en) * 1994-07-05 1996-07-09 Motorola, Inc. Data processor with future file with parallel update and method of operation
US5623615A (en) * 1994-08-04 1997-04-22 International Business Machines Corporation Circuit and method for reducing prefetch cycles on microprocessors
EP0698884A1 (en) * 1994-08-24 1996-02-28 Advanced Micro Devices Inc. Memory array for microprocessor cache
US5928357A (en) * 1994-09-15 1999-07-27 Intel Corporation Circuitry and method for performing branching without pipeline delay
US5721695A (en) * 1994-10-17 1998-02-24 Advanced Micro Devices, Inc. Simulation by emulating level sensitive latches with edge trigger latches
US5603045A (en) * 1994-12-16 1997-02-11 Vlsi Technology, Inc. Microprocessor system having instruction cache with reserved branch target section
US6237082B1 (en) 1995-01-25 2001-05-22 Advanced Micro Devices, Inc. Reorder buffer configured to allocate storage for instruction results corresponding to predefined maximum number of concurrently receivable instructions independent of a number of instructions received
US5878244A (en) * 1995-01-25 1999-03-02 Advanced Micro Devices, Inc. Reorder buffer configured to allocate storage capable of storing results corresponding to a maximum number of concurrently receivable instructions regardless of a number of instructions received
US5903741A (en) * 1995-01-25 1999-05-11 Advanced Micro Devices, Inc. Method of allocating a fixed reorder buffer storage line for execution results regardless of a number of concurrently dispatched instructions
US5901302A (en) * 1995-01-25 1999-05-04 Advanced Micro Devices, Inc. Superscalar microprocessor having symmetrical, fixed issue positions each configured to execute a particular subset of instructions
US5933860A (en) * 1995-02-10 1999-08-03 Digital Equipment Corporation Multiprobe instruction cache with instruction-based probe hint generation and training whereby the cache bank or way to be accessed next is predicted
US5708788A (en) * 1995-03-03 1998-01-13 Fujitsu, Ltd. Method for adjusting fetch program counter in response to the number of instructions fetched and issued
US5737550A (en) * 1995-03-28 1998-04-07 Advanced Micro Devices, Inc. Cache memory to processor bus interface and method thereof
US5822574A (en) * 1995-04-12 1998-10-13 Advanced Micro Devices, Inc. Functional unit with a pointer for mispredicted resolution, and a superscalar microprocessor employing the same
US5764946A (en) * 1995-04-12 1998-06-09 Advanced Micro Devices Superscalar microprocessor employing a way prediction unit to predict the way of an instruction fetch address and to concurrently provide a branch prediction address corresponding to the fetch address
US5878255A (en) * 1995-06-07 1999-03-02 Advanced Micro Devices, Inc. Update unit for providing a delayed update to a branch prediction array
US5875324A (en) * 1995-06-07 1999-02-23 Advanced Micro Devices, Inc. Superscalar microprocessor which delays update of branch prediction information in response to branch misprediction until a subsequent idle clock
US5968169A (en) * 1995-06-07 1999-10-19 Advanced Micro Devices, Inc. Superscalar microprocessor stack structure for judging validity of predicted subroutine return addresses
US6112019A (en) * 1995-06-12 2000-08-29 Georgia Tech Research Corp. Distributed instruction queue
US5828895A (en) * 1995-09-20 1998-10-27 International Business Machines Corporation Methods and system for predecoding instructions in a superscalar data processing system
DE69629495D1 (en) 1995-10-06 2003-09-18 Advanced Micro Devices Inc Uniformed multifunctional operation distributor for disordered command execution in a super-scalar processor
GB9521980D0 (en) * 1995-10-26 1996-01-03 Sgs Thomson Microelectronics Branch target buffer
US5881278A (en) * 1995-10-30 1999-03-09 Advanced Micro Devices, Inc. Return address prediction system which adjusts the contents of return stack storage to enable continued prediction after a mispredicted branch
US5796974A (en) * 1995-11-07 1998-08-18 Advanced Micro Devices, Inc. Microcode patching apparatus and method
US5835744A (en) * 1995-11-20 1998-11-10 Advanced Micro Devices, Inc. Microprocessor configured to swap operands in order to minimize dependency checking logic
US5713039A (en) * 1995-12-05 1998-01-27 Advanced Micro Devices, Inc. Register file having multiple register storages for storing data from multiple data streams
US5864707A (en) * 1995-12-11 1999-01-26 Advanced Micro Devices, Inc. Superscalar microprocessor configured to predict return addresses from a return stack storage
US5732235A (en) * 1996-01-25 1998-03-24 International Business Machines Corporation Method and system for minimizing the number of cycles required to execute semantic routines
US5884059A (en) * 1996-01-26 1999-03-16 Advanced Micro Devices, Inc. Unified multi-function operation scheduler for out-of-order execution in a superscalar processor
US5742805A (en) * 1996-02-15 1998-04-21 Fujitsu Ltd. Method and apparatus for a single history register based branch predictor in a superscalar microprocessor
US5752259A (en) * 1996-03-26 1998-05-12 Advanced Micro Devices, Inc. Instruction cache configured to provide instructions to a microprocessor having a clock cycle time less than a cache access time of said instruction cache
US5835511A (en) * 1996-05-17 1998-11-10 Advanced Micro Devices, Inc. Method and mechanism for checking integrity of byte enable signals
US5918056A (en) * 1996-05-17 1999-06-29 Advanced Micro Devices, Inc. Segmentation suspend mode for real-time interrupt support
US6108769A (en) 1996-05-17 2000-08-22 Advanced Micro Devices, Inc. Dependency table for reducing dependency checking hardware
US5761490A (en) * 1996-05-28 1998-06-02 Hewlett-Packard Company Changing the meaning of a pre-decode bit in a cache memory depending on branch prediction mode
US6049863A (en) * 1996-07-24 2000-04-11 Advanced Micro Devices, Inc. Predecoding technique for indicating locations of opcode bytes in variable byte-length instructions within a superscalar microprocessor
US5903740A (en) * 1996-07-24 1999-05-11 Advanced Micro Devices, Inc. Apparatus and method for retiring instructions in excess of the number of accessible write ports
US5900013A (en) * 1996-07-26 1999-05-04 Advanced Micro Devices, Inc. Dual comparator scheme for detecting a wrap-around condition and generating a cancel signal for removing wrap-around buffer entries
US5872943A (en) * 1996-07-26 1999-02-16 Advanced Micro Devices, Inc. Apparatus for aligning instructions using predecoded shift amounts
US5872951A (en) * 1996-07-26 1999-02-16 Advanced Micro Design, Inc. Reorder buffer having a future file for storing speculative instruction execution results
US5946468A (en) * 1996-07-26 1999-08-31 Advanced Micro Devices, Inc. Reorder buffer having an improved future file for storing speculative instruction execution results
US5915110A (en) * 1996-07-26 1999-06-22 Advanced Micro Devices, Inc. Branch misprediction recovery in a reorder buffer having a future file
US5765016A (en) * 1996-09-12 1998-06-09 Advanced Micro Devices, Inc. Reorder buffer configured to store both speculative and committed register states
US5822575A (en) * 1996-09-12 1998-10-13 Advanced Micro Devices, Inc. Branch prediction storage for storing branch prediction information such that a corresponding tag may be routed with the branch instruction
US5794028A (en) * 1996-10-17 1998-08-11 Advanced Micro Devices, Inc. Shared branch prediction structure
US5850543A (en) * 1996-10-30 1998-12-15 Texas Instruments Incorporated Microprocessor with speculative instruction pipelining storing a speculative register value within branch target buffer for use in speculatively executing instructions after a return
US5918044A (en) * 1996-10-31 1999-06-29 International Business Machines Corporation Apparatus and method for instruction fetching using a multi-port instruction cache directory
US5920710A (en) * 1996-11-18 1999-07-06 Advanced Micro Devices, Inc. Apparatus and method for modifying status bits in a reorder buffer with a large speculative state
US5870579A (en) * 1996-11-18 1999-02-09 Advanced Micro Devices, Inc. Reorder buffer including a circuit for selecting a designated mask corresponding to an instruction that results in an exception
US5978906A (en) * 1996-11-19 1999-11-02 Advanced Micro Devices, Inc. Branch selectors associated with byte ranges within an instruction cache for rapidly identifying branch predictions
US5995749A (en) 1996-11-19 1999-11-30 Advanced Micro Devices, Inc. Branch prediction mechanism employing branch selectors to select a branch prediction
US5954816A (en) * 1996-11-19 1999-09-21 Advanced Micro Devices, Inc. Branch selector prediction
US6175906B1 (en) 1996-12-06 2001-01-16 Advanced Micro Devices, Inc. Mechanism for fast revalidation of virtual tags
US5870580A (en) * 1996-12-13 1999-02-09 Advanced Micro Devices, Inc. Decoupled forwarding reorder buffer configured to allocate storage in chunks for instructions having unresolved dependencies
US5881305A (en) * 1996-12-13 1999-03-09 Advanced Micro Devices, Inc. Register rename stack for a microprocessor
US5862065A (en) * 1997-02-13 1999-01-19 Advanced Micro Devices, Inc. Method and circuit for fast generation of zero flag condition code in a microprocessor-based computer
US5768555A (en) * 1997-02-20 1998-06-16 Advanced Micro Devices, Inc. Reorder buffer employing last in buffer and last in line bits
US5974538A (en) * 1997-02-21 1999-10-26 Wilmot, Ii; Richard Byron Method and apparatus for annotating operands in a computer system with source instruction identifiers
US6141740A (en) * 1997-03-03 2000-10-31 Advanced Micro Devices, Inc. Apparatus and method for microcode patching for generating a next address
US6233672B1 (en) 1997-03-06 2001-05-15 Advanced Micro Devices, Inc. Piping rounding mode bits with floating point instructions to eliminate serialization
US5850532A (en) * 1997-03-10 1998-12-15 Advanced Micro Devices, Inc. Invalid instruction scan unit for detecting invalid predecode data corresponding to instructions being fetched
US5852727A (en) * 1997-03-10 1998-12-22 Advanced Micro Devices, Inc. Instruction scanning unit for locating instructions via parallel scanning of start and end byte information
US5968163A (en) 1997-03-10 1999-10-19 Advanced Micro Devices, Inc. Microcode scan unit for scanning microcode instructions using predecode data
US5983321A (en) * 1997-03-12 1999-11-09 Advanced Micro Devices, Inc. Cache holding register for receiving instruction packets and for providing the instruction packets to a predecode unit and instruction cache
US5859992A (en) * 1997-03-12 1999-01-12 Advanced Micro Devices, Inc. Instruction alignment using a dispatch list and a latch list
US5930492A (en) * 1997-03-19 1999-07-27 Advanced Micro Devices, Inc. Rapid pipeline control using a control word and a steering word
US5887185A (en) * 1997-03-19 1999-03-23 Advanced Micro Devices, Inc. Interface for coupling a floating point unit to a reorder buffer
US5828873A (en) * 1997-03-19 1998-10-27 Advanced Micro Devices, Inc. Assembly queue for a floating point unit
US5859998A (en) * 1997-03-19 1999-01-12 Advanced Micro Devices, Inc. Hierarchical microcode implementation of floating point instructions for a microprocessor
US5987599A (en) * 1997-03-28 1999-11-16 Intel Corporation Target instructions prefetch cache
US5987235A (en) * 1997-04-04 1999-11-16 Advanced Micro Devices, Inc. Method and apparatus for predecoding variable byte length instructions for fast scanning of instructions
US5901076A (en) * 1997-04-16 1999-05-04 Advanced Micro Designs, Inc. Ripple carry shifter in a floating point arithmetic unit of a microprocessor
US6003128A (en) * 1997-05-01 1999-12-14 Advanced Micro Devices, Inc. Number of pipeline stages and loop length related counter differential based end-loop prediction
US6122729A (en) 1997-05-13 2000-09-19 Advanced Micro Devices, Inc. Prefetch buffer which stores a pointer indicating an initial predecode position
US5845101A (en) * 1997-05-13 1998-12-01 Advanced Micro Devices, Inc. Prefetch buffer for storing instructions prior to placing the instructions in an instruction cache
US6016543A (en) * 1997-05-14 2000-01-18 Mitsubishi Denki Kabushiki Kaisha Microprocessor for controlling the conditional execution of instructions
US6073230A (en) * 1997-06-11 2000-06-06 Advanced Micro Devices, Inc. Instruction fetch unit configured to provide sequential way prediction for sequential instruction fetches
US5872946A (en) * 1997-06-11 1999-02-16 Advanced Micro Devices, Inc. Instruction alignment unit employing dual instruction queues for high frequency instruction dispatch
US6009511A (en) * 1997-06-11 1999-12-28 Advanced Micro Devices, Inc. Apparatus and method for tagging floating point operands and results for rapid detection of special floating point numbers
US5940602A (en) * 1997-06-11 1999-08-17 Advanced Micro Devices, Inc. Method and apparatus for predecoding variable byte length instructions for scanning of a number of RISC operations
US5983337A (en) * 1997-06-12 1999-11-09 Advanced Micro Devices, Inc. Apparatus and method for patching an instruction by providing a substitute instruction or instructions from an external memory responsive to detecting an opcode of the instruction
US5898865A (en) * 1997-06-12 1999-04-27 Advanced Micro Devices, Inc. Apparatus and method for predicting an end of loop for string instructions
US5933629A (en) * 1997-06-12 1999-08-03 Advanced Micro Devices, Inc. Apparatus and method for detecting microbranches early
US5933626A (en) * 1997-06-12 1999-08-03 Advanced Micro Devices, Inc. Apparatus and method for tracing microprocessor instructions
US6012125A (en) * 1997-06-20 2000-01-04 Advanced Micro Devices, Inc. Superscalar microprocessor including a decoded instruction cache configured to receive partially decoded instructions
US5978901A (en) * 1997-08-21 1999-11-02 Advanced Micro Devices, Inc. Floating point and multimedia unit with data type reclassification capability
US6101577A (en) * 1997-09-15 2000-08-08 Advanced Micro Devices, Inc. Pipelined instruction cache and branch prediction mechanism therefor
US6185676B1 (en) * 1997-09-30 2001-02-06 Intel Corporation Method and apparatus for performing early branch prediction in a microprocessor
US5931943A (en) * 1997-10-21 1999-08-03 Advanced Micro Devices, Inc. Floating point NaN comparison
US6032252A (en) * 1997-10-28 2000-02-29 Advanced Micro Devices, Inc. Apparatus and method for efficient loop control in a superscalar microprocessor
US5974542A (en) * 1997-10-30 1999-10-26 Advanced Micro Devices, Inc. Branch prediction unit which approximates a larger number of branch predictions using a smaller number of branch predictions and an alternate target indication
US6230259B1 (en) 1997-10-31 2001-05-08 Advanced Micro Devices, Inc. Transparent extended state save
US6157996A (en) * 1997-11-13 2000-12-05 Advanced Micro Devices, Inc. Processor programably configurable to execute enhanced variable byte length instructions including predicated execution, three operand addressing, and increased register space
US6199154B1 (en) 1997-11-17 2001-03-06 Advanced Micro Devices, Inc. Selecting cache to fetch in multi-level cache system based on fetch address source and pre-fetching additional data to the cache for future access
US6256728B1 (en) 1997-11-17 2001-07-03 Advanced Micro Devices, Inc. Processor configured to selectively cancel instructions from its pipeline responsive to a predicted-taken short forward branch instruction
US6079005A (en) * 1997-11-20 2000-06-20 Advanced Micro Devices, Inc. Microprocessor including virtual address branch prediction and current page register to provide page portion of virtual and physical fetch address
US6154818A (en) * 1997-11-20 2000-11-28 Advanced Micro Devices, Inc. System and method of controlling access to privilege partitioned address space for a model specific register file
US6516395B1 (en) 1997-11-20 2003-02-04 Advanced Micro Devices, Inc. System and method for controlling access to a privilege-partitioned address space with a fixed set of attributes
US6079003A (en) * 1997-11-20 2000-06-20 Advanced Micro Devices, Inc. Reverse TLB for providing branch target address in a microprocessor having a physically-tagged cache
US5974432A (en) * 1997-12-05 1999-10-26 Advanced Micro Devices, Inc. On-the-fly one-hot encoding of leading zero count
US5870578A (en) * 1997-12-09 1999-02-09 Advanced Micro Devices, Inc. Workload balancing in a microprocessor for reduced instruction dispatch stalling
US6016533A (en) * 1997-12-16 2000-01-18 Advanced Micro Devices, Inc. Way prediction logic for cache array
US6157986A (en) * 1997-12-16 2000-12-05 Advanced Micro Devices, Inc. Fast linear tag validation unit for use in microprocessor
US6016545A (en) * 1997-12-16 2000-01-18 Advanced Micro Devices, Inc. Reduced size storage apparatus for storing cache-line-related data in a high frequency microprocessor
US6112018A (en) 1997-12-18 2000-08-29 Advanced Micro Devices, Inc. Apparatus for exchanging two stack registers
US6018798A (en) * 1997-12-18 2000-01-25 Advanced Micro Devices, Inc. Floating point unit using a central window for storing instructions capable of executing multiple instructions in a single clock cycle
US6112296A (en) * 1997-12-18 2000-08-29 Advanced Micro Devices, Inc. Floating point stack manipulation using a register map and speculative top of stack values
US5954814A (en) * 1997-12-19 1999-09-21 Intel Corporation System for using a branch prediction unit to achieve serialization by forcing a branch misprediction to flush a pipeline
US6141745A (en) * 1998-04-30 2000-10-31 Advanced Micro Devices, Inc. Functional bit identifying a prefix byte via a particular state regardless of type of instruction
US6175908B1 (en) 1998-04-30 2001-01-16 Advanced Micro Devices, Inc. Variable byte-length instructions using state of function bit of second byte of plurality of instructions bytes as indicative of whether first byte is a prefix byte
US6230262B1 (en) 1998-07-31 2001-05-08 Advanced Micro Devices, Inc. Processor configured to selectively free physical registers upon retirement of instructions
US6119223A (en) * 1998-07-31 2000-09-12 Advanced Micro Devices, Inc. Map unit having rapid misprediction recovery
US6122656A (en) * 1998-07-31 2000-09-19 Advanced Micro Devices, Inc. Processor configured to map logical register numbers to physical register numbers using virtual register numbers
US6230260B1 (en) 1998-09-01 2001-05-08 International Business Machines Corporation Circuit arrangement and method of speculative instruction execution utilizing instruction history caching
US6205544B1 (en) 1998-12-21 2001-03-20 Intel Corporation Decomposition of instructions into branch and sequential code sections
US6442681B1 (en) * 1998-12-28 2002-08-27 Bull Hn Information Systems Inc. Pipelined central processor managing the execution of instructions with proximate successive branches in a cache-based data processing system while performing block mode transfer predictions
US6957327B1 (en) * 1998-12-31 2005-10-18 Stmicroelectronics, Inc. Block-based branch target buffer
US6247097B1 (en) * 1999-01-22 2001-06-12 International Business Machines Corporation Aligned instruction cache handling of instruction fetches across multiple predicted branch instructions
US6516462B1 (en) * 1999-02-17 2003-02-04 Elbrus International Cache miss saving for speculation load operation
DE19945940C2 (en) * 1999-09-24 2002-01-17 Infineon Technologies Ag Method and apparatus for processing conditional branch instructions in a pipelined processor computer architecture
US6438664B1 (en) 1999-10-27 2002-08-20 Advanced Micro Devices, Inc. Microcode patch device and method for patching microcode using match registers and patch routines
US6442707B1 (en) 1999-10-29 2002-08-27 Advanced Micro Devices, Inc. Alternate fault handler
US6981132B2 (en) 2000-08-09 2005-12-27 Advanced Micro Devices, Inc. Uniform register addressing using prefix byte
US6877084B1 (en) 2000-08-09 2005-04-05 Advanced Micro Devices, Inc. Central processing unit (CPU) accessing an extended register set in an extended register mode
US6732253B1 (en) * 2000-11-13 2004-05-04 Chipwrights Design, Inc. Loop handling for single instruction multiple datapath processor architectures
US6931518B1 (en) 2000-11-28 2005-08-16 Chipwrights Design, Inc. Branching around conditional processing if states of all single instruction multiple datapaths are disabled and the computer program is non-deterministic
US7493607B2 (en) 2002-07-09 2009-02-17 Bluerisc Inc. Statically speculative compilation and execution
US20050050278A1 (en) * 2003-09-03 2005-03-03 Advanced Micro Devices, Inc. Low power way-predicted cache
US7117290B2 (en) * 2003-09-03 2006-10-03 Advanced Micro Devices, Inc. MicroTLB and micro tag for reducing power in a processor
US20050114850A1 (en) 2003-10-29 2005-05-26 Saurabh Chheda Energy-focused re-compilation of executables and hardware mechanisms based on compiler-architecture interaction and compiler-inserted control
US7996671B2 (en) 2003-11-17 2011-08-09 Bluerisc Inc. Security of program executables and microprocessors based on compiler-architecture interaction
US8607209B2 (en) 2004-02-04 2013-12-10 Bluerisc Inc. Energy-focused compiler-assisted branch prediction
US9047094B2 (en) * 2004-03-31 2015-06-02 Icera Inc. Apparatus and method for separate asymmetric control processing and data path processing in a dual path processor
US8484441B2 (en) * 2004-03-31 2013-07-09 Icera Inc. Apparatus and method for separate asymmetric control processing and data path processing in a configurable dual path processor that supports instructions having different bit widths
US7949856B2 (en) * 2004-03-31 2011-05-24 Icera Inc. Method and apparatus for separate control processing and data path processing in a dual path processor with a shared load/store unit
JP3926809B2 (en) * 2004-07-27 2007-06-06 富士通株式会社 Branch instruction control device and control method.
WO2006026510A2 (en) 2004-08-30 2006-03-09 Texas Instruments Incorporated Methods and apparatus for branch prediction and processing of microprocessor instructions and the like
US8578134B1 (en) * 2005-04-04 2013-11-05 Globalfoundries Inc. System and method for aligning change-of-flow instructions in an instruction buffer
US8161252B1 (en) * 2005-08-01 2012-04-17 Nvidia Corporation Memory interface with dynamic selection among mirrored storage locations
US7447883B2 (en) * 2006-08-10 2008-11-04 Arm Limited Allocation of branch target cache resources in dependence upon program instructions within an instruction queue
US7640422B2 (en) * 2006-08-16 2009-12-29 Qualcomm Incorporated System for reducing number of lookups in a branch target address cache by storing retrieved BTAC addresses into instruction cache
US20080126766A1 (en) 2006-11-03 2008-05-29 Saurabh Chheda Securing microprocessors against information leakage and physical tampering
US20080154379A1 (en) * 2006-12-22 2008-06-26 Musculoskeletal Transplant Foundation Interbody fusion hybrid graft
WO2009101562A2 (en) * 2008-02-11 2009-08-20 Nxp B.V. Method of program obfuscation and processing device for executing obfuscated programs
US8181005B2 (en) * 2008-09-05 2012-05-15 Advanced Micro Devices, Inc. Hybrid branch prediction device with sparse and dense prediction caches
US20110093658A1 (en) * 2009-10-19 2011-04-21 Zuraski Jr Gerald D Classifying and segregating branch targets
US9916252B2 (en) 2015-05-19 2018-03-13 Linear Algebra Technologies Limited Systems and methods for addressing a cache with split-indexes

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4200927A (en) * 1978-01-03 1980-04-29 International Business Machines Corporation Multi-instruction stream branch processing mechanism
US4295193A (en) * 1979-06-29 1981-10-13 International Business Machines Corporation Machine for multiple instruction execution
US4430706A (en) * 1980-10-27 1984-02-07 Burroughs Corporation Branch prediction apparatus and method for a data processing system
US4477872A (en) * 1982-01-15 1984-10-16 International Business Machines Corporation Decode history table for conditional branch instructions
US4604691A (en) * 1982-09-07 1986-08-05 Nippon Electric Co., Ltd. Data processing system having branch instruction prefetching performance
DE3382350D1 (en) * 1982-11-17 1991-08-29 Nec Corp An arrangement for pre-fetching instructions with prediction of a branch destination address.
US4807115A (en) * 1983-10-07 1989-02-21 Cornell Research Foundation, Inc. Instruction issuing mechanism for processors with multiple functional units
US4764861A (en) * 1984-02-08 1988-08-16 Nec Corporation Instruction fpefetching device with prediction of a branch destination for each branch count instruction
US4755966A (en) * 1985-06-28 1988-07-05 Hewlett-Packard Company Bidirectional branch prediction and optimization
JP2603626B2 (en) * 1987-01-16 1997-04-23 三菱電機株式会社 Data processing equipment
US4894772A (en) * 1987-07-31 1990-01-16 Prime Computer, Inc. Method and apparatus for qualifying branch cache entries
US4860197A (en) * 1987-07-31 1989-08-22 Prime Computer, Inc. Branch cache system with instruction boundary determination independent of parcel boundary
US4943908A (en) * 1987-12-02 1990-07-24 International Business Machines Corporation Multiple branch analyzer for prefetching cache lines

Also Published As

Publication number Publication date
EP0401992A3 (en) 1992-12-30
ES2111528T3 (en) 1998-03-16
EP0401992B1 (en) 1998-01-28
DE69031991D1 (en) 1998-03-05
JP2889955B2 (en) 1999-05-10
JPH0334024A (en) 1991-02-14
EP0401992A2 (en) 1990-12-12
US5136697A (en) 1992-08-04
DE69031991T2 (en) 1998-08-20
USRE35794E (en) 1998-05-12

Similar Documents

Publication Publication Date Title
DE69131595D1 (en) Method and apparatus for dynamic leveling
DE3609681A1 (en) Apparatus and method for duennfilmerzeugung
DE69329950T2 (en) Apparatus and method for determining the concentration of calcium
DE69315351T2 (en) Device and method for displaying emboli by means of ultrasonic
DE3881872T2 (en) Method and apparatus for static quasiresonanzstromartleistungsumwandlung.
DE68928192T2 (en) Apparatus and method for position detection
DE3872932T2 (en) Apparatus and method for detection oberflaechenfehler.
DE3750473T2 (en) Apparatus and method for solid phase immunodiffusion assay.
DE68902250T2 (en) Method and apparatus for tiefkuehlung of products.
DE3776056D1 (en) Method and apparatus for daempfungsregelung.
DE69331024T2 (en) Methods and apparatus for the formation of logs
DE68921813T2 (en) Method and device for reduction of color separation rules.
DE69011051T2 (en) Method and apparatus for Heizbearbeitung of suture thread.
DE3850287T2 (en) Device and method for separating blood phases.
DE68901089D1 (en) Method and apparatus for c2 rueckgewinnung.
DE69221980D1 (en) Method and apparatus sequences dns-nucleotide for the determination of
DE69228823T2 (en) Apparatus and method for the examination of the cerebral bio-potentials
DE3751823T2 (en) Physical process for deodorizing and for the simultaneous reduction of cholesterol-fats or oils
DE3606661A1 (en) Method and apparatus for bilduebertragung
AT106607T (en) Ball-bond method and device for execution thereof.
DE3854334T2 (en) Method and apparatus for determination of substances.
DE69218536D1 (en) Method and apparatus for Spektrenvergleichung
DE3667864D1 (en) Device and for wellenlaengenselektion process.
DE69310375D1 (en) Apparatus and method for selbstbraünerung
DE3769430D1 (en) Method and test device for the evidence of explosives.