AT150191T - A method and data processing unit processor pipeline for preprocessing of implied specifiers in an - Google Patents

A method and data processing unit processor pipeline for preprocessing of implied specifiers in an

Info

Publication number
AT150191T
AT150191T AT89308996T AT89308996T AT150191T AT 150191 T AT150191 T AT 150191T AT 89308996 T AT89308996 T AT 89308996T AT 89308996 T AT89308996 T AT 89308996T AT 150191 T AT150191 T AT 150191T
Authority
AT
Austria
Prior art keywords
preprocessing
processing unit
data processing
method
processor pipeline
Prior art date
Application number
AT89308996T
Other languages
German (de)
Inventor
David B Fite
Mark A Firstenberg
John E Murray
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US07/306,846 priority Critical patent/US5142633A/en
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Publication of AT150191T publication Critical patent/AT150191T/en

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003Arrangements for executing specific machine instructions
    • G06F9/3005Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30054Unconditional branch instructions
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/30149Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016Decoding the operand specifier, e.g. specifier format
    • G06F9/30163Decoding the operand specifier, e.g. specifier format with implied specifier, e.g. top of stack
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016Decoding the operand specifier, e.g. specifier format
    • G06F9/30167Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017Runtime instruction translation, e.g. macros
    • G06F9/30178Runtime instruction translation, e.g. macros of compressed or encrypted instructions
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802Instruction prefetching
    • G06F9/3816Instruction alignment, e.g. cache line crossing
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3818Decoding for concurrent execution
    • G06F9/3822Parallel decoding, e.g. parallel decode units
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3824Operand accessing
AT89308996T 1989-02-03 1989-09-05 A method and data processing unit processor pipeline for preprocessing of implied specifiers in an AT150191T (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US07/306,846 US5142633A (en) 1989-02-03 1989-02-03 Preprocessing implied specifiers in a pipelined processor

Publications (1)

Publication Number Publication Date
AT150191T true AT150191T (en) 1997-03-15

Family

ID=23187130

Family Applications (1)

Application Number Title Priority Date Filing Date
AT89308996T AT150191T (en) 1989-02-03 1989-09-05 A method and data processing unit processor pipeline for preprocessing of implied specifiers in an

Country Status (6)

Country Link
US (1) US5142633A (en)
EP (1) EP0380849B1 (en)
JP (1) JPH031235A (en)
AT (1) AT150191T (en)
CA (1) CA1323940C (en)
DE (2) DE68927855T2 (en)

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US5471591A (en) * 1990-06-29 1995-11-28 Digital Equipment Corporation Combined write-operand queue and read-after-write dependency scoreboard
DE69130138D1 (en) * 1990-06-29 1998-10-15 Digital Equipment Corp Branch prediction unit for high-performance processor
JP2956707B2 (en) * 1990-10-29 1999-10-04 富士通株式会社 The information processing apparatus
US5493687A (en) 1991-07-08 1996-02-20 Seiko Epson Corporation RISC microprocessor architecture implementing multiple typed register sets
US5539911A (en) * 1991-07-08 1996-07-23 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US5321810A (en) * 1991-08-21 1994-06-14 Digital Equipment Corporation Address method for computer graphics system
AU2509192A (en) * 1991-08-21 1993-03-16 Digital Equipment Corporation Address method for computer graphics system
WO1993020505A2 (en) 1992-03-31 1993-10-14 Seiko Epson Corporation Superscalar risc instruction scheduling
DE69308548T2 (en) 1992-05-01 1997-06-12 Seiko Epson Corp Device and method for command statements in a superscalar processor.
JP3531166B2 (en) 1992-12-31 2004-05-24 セイコーエプソン株式会社 Register renaming system and method
US5604912A (en) * 1992-12-31 1997-02-18 Seiko Epson Corporation System and method for assigning tags to instructions to control instruction execution
US5628021A (en) * 1992-12-31 1997-05-06 Seiko Epson Corporation System and method for assigning tags to control instruction processing in a superscalar processor
US5428807A (en) * 1993-06-17 1995-06-27 Digital Equipment Corporation Method and apparatus for propagating exception conditions of a computer system
US6704861B1 (en) 1993-06-17 2004-03-09 Hewlett-Packard Development Company, L.P. Mechanism for executing computer instructions in parallel
US5420990A (en) * 1993-06-17 1995-05-30 Digital Equipment Corporation Mechanism for enforcing the correct order of instruction execution
US5421022A (en) * 1993-06-17 1995-05-30 Digital Equipment Corporation Apparatus and method for speculatively executing instructions in a computer system
US6101597A (en) * 1993-12-30 2000-08-08 Intel Corporation Method and apparatus for maximum throughput scheduling of dependent operations in a pipelined processor
US6393550B1 (en) * 1993-12-30 2002-05-21 Intel Corporation Method and apparatus for pipeline streamlining where resources are immediate or certainly retired
US5553256A (en) * 1994-02-28 1996-09-03 Intel Corporation Apparatus for pipeline streamlining where resources are immediate or certainly retired
US5584037A (en) * 1994-03-01 1996-12-10 Intel Corporation Entry allocation in a circular buffer
GB9412434D0 (en) 1994-06-21 1994-08-10 Inmos Ltd Computer instruction compression
JP3493369B2 (en) * 1994-12-13 2004-02-03 株式会社ルネサステクノロジ Computer
US6128720A (en) * 1994-12-29 2000-10-03 International Business Machines Corporation Distributed processing array with component processors performing customized interpretation of instructions
US6041403A (en) * 1996-09-27 2000-03-21 Intel Corporation Method and apparatus for generating a microinstruction responsive to the specification of an operand, in addition to a microinstruction based on the opcode, of a macroinstruction
US6192463B1 (en) 1997-10-07 2001-02-20 Microchip Technology, Inc. Processor architecture scheme which uses virtual address registers to implement different addressing modes and method therefor
US6098160A (en) * 1997-10-28 2000-08-01 Microchip Technology Incorporated Data pointer for outputting indirect addressing mode addresses within a single cycle and method therefor
US6748589B1 (en) 1999-10-20 2004-06-08 Transmeta Corporation Method for increasing the speed of speculative execution
AU4551101A (en) * 2000-03-10 2001-09-24 Arc Internat Plc Method and apparatus for enhancing the performance of a pipelined data processor
GB2363869B (en) 2000-06-20 2004-06-23 Element 14 Inc Register addressing
US9304932B2 (en) 2012-12-20 2016-04-05 Qualcomm Incorporated Instruction cache having a multi-bit way prediction mask
CN107533461A (en) * 2015-04-24 2018-01-02 优创半导体科技有限公司 With the computer processor for the different registers to memory addressing

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US4162519A (en) * 1975-01-20 1979-07-24 Nixdorf Computer Ag Data processor with address allocation to operations
JPS5931734B2 (en) * 1977-10-25 1984-08-03 Digital Equipment Corp
JPS5747449B2 (en) * 1978-01-26 1982-10-09
US4241399A (en) * 1978-10-25 1980-12-23 Digital Equipment Corporation Calling instructions for a data processing system
US4493020A (en) * 1980-05-06 1985-01-08 Burroughs Corporation Microprogrammed digital data processor employing microinstruction tasking and dynamic register allocation
CA1174370A (en) * 1980-05-19 1984-09-11 Hidekazu Matsumoto Data processing unit with pipelined operands
JPS6232503B2 (en) * 1982-02-26 1987-07-15 Hitachi Ltd
US4873629A (en) * 1984-06-20 1989-10-10 Convex Computer Corporation Instruction processing unit for computer
US4789925A (en) * 1985-07-31 1988-12-06 Unisys Corporation Vector data logical usage conflict detection
US4890218A (en) * 1986-07-02 1989-12-26 Raytheon Company Variable length instruction decoding apparatus having cross coupled first and second microengines
US4891753A (en) * 1986-11-26 1990-01-02 Intel Corporation Register scorboarding on a microprocessor chip
JPH06100967B2 (en) * 1987-06-10 1994-12-12 三菱電機株式会社 Data processing apparatus and processing method with pipeline processing mechanism
JPH07120278B2 (en) * 1988-07-04 1995-12-20 三菱電機株式会社 Data processing equipment

Also Published As

Publication number Publication date
DE68927855T2 (en) 1997-10-16
JPH031235A (en) 1991-01-07
CA1323940C (en) 1993-11-02
EP0380849A2 (en) 1990-08-08
EP0380849B1 (en) 1997-03-12
DE68927855D1 (en) 1997-04-17
EP0380849A3 (en) 1992-08-12
US5142633A (en) 1992-08-25

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