WO2010072113A1 - 一种存储方法、存储系统及控制器 - Google Patents

一种存储方法、存储系统及控制器 Download PDF

Info

Publication number
WO2010072113A1
WO2010072113A1 PCT/CN2009/075168 CN2009075168W WO2010072113A1 WO 2010072113 A1 WO2010072113 A1 WO 2010072113A1 CN 2009075168 W CN2009075168 W CN 2009075168W WO 2010072113 A1 WO2010072113 A1 WO 2010072113A1
Authority
WO
WIPO (PCT)
Prior art keywords
controller
pcie
storage devices
modules
storage
Prior art date
Application number
PCT/CN2009/075168
Other languages
English (en)
French (fr)
Inventor
张巍
吕先红
王奇
范瑞琦
Original Assignee
成都市华为赛门铁克科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 成都市华为赛门铁克科技有限公司 filed Critical 成都市华为赛门铁克科技有限公司
Priority to EP09834066A priority Critical patent/EP2378430A4/en
Publication of WO2010072113A1 publication Critical patent/WO2010072113A1/zh
Priority to US13/168,552 priority patent/US8296476B2/en

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0628Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0658Controller construction arrangements
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0602Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0626Reducing size or complexity of storage systems
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0668Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671In-line storage system

Definitions

  • the present invention relates to the field of information technology, and in particular, to a storage method, a storage system, and a controller.
  • Controller-0 and controller-1 are connected through a mirrored channel, which is respectively connected to the mirror chip of controller-0 and the mirror chip of controller-1, and the server exchanges peripherals with controller-0 through the switching network.
  • the Peripheral Component Interconnection Express (PCIE) interface card is connected to the PCIE interface card of the controller_1, and the controller-0 is connected to the hard disk of the traditional interface through the hard disk expansion chip, and the controller-1 is also connected.
  • the hard disk expansion chip is connected to the hard disk of the traditional interface.
  • the hard disk expansion chip is connected to the PCIE switch chip (Switch) through the hard disk controller, and the PCIE switch chip is respectively connected with the PCIE interface card, the mirror chip and the hard disk controller. It is connected to the memory through a central processing unit (CPU) and a chipset.
  • CPU central processing unit
  • the server sends a request, the request is sent to the controller through the preferred (most recent) path, and it is determined whether the controller is at the home controller, and when the controller is the home controller, the controller Processing the request; when the controller is not the home controller, forwarding to the home controller, causing the home controller to process the request.
  • the home controller of LUN_0 is controller-0.
  • controller-1 is not the home of LUN_0.
  • the controller forwards the request for LUN_0 to the home controller of LUN_0, the request for LUN_0 is forwarded to the controller_0 through the mirroring channel, and the request is processed by the controller-0.
  • Controller-0 and controller-1 have independent PCIE interface cards, but cannot be used by the peer controller, resulting in waste of resources.
  • the traditional hard disk must be connected to the storage controller through the hard disk controller and the hard disk expansion chip, and the use of the hard disk controller and the hard disk expansion chip causes the controller cost to be high. Summary of the invention
  • Embodiments of the present invention provide a storage method, a storage system, and a controller, so that a storage device and a PCIE 10 module are shared between controllers.
  • an embodiment of the present invention provides a storage method, which is applied to a system including at least one controller, at least two peripheral components interconnecting a standard PCIE input and output 10 module, and at least two storage devices. At least two storage devices are connected by a PCIE switch chip of the at least one controller, the at least two peripheral components interconnecting a standard PCIE input output 10 module connected by a PCIE switch chip of the at least one controller, the method Includes:
  • An embodiment of the present invention provides a storage system, including: at least one controller, at least two a PCIE 10 module and at least two storage devices, the at least two storage devices being connected by a PCIE switch chip of the at least one controller, wherein the at least two PCIE 10 modules are connected by a PCIE switch chip of the at least one controller , among them:
  • a controller configured to receive, by the at least two PCIE 10 modules, a request message from a server, and access the at least two storage devices according to the request message;
  • the at least two storage devices are configured to store information corresponding to the request message.
  • the embodiment of the present invention provides a controller, which is applied to a system including at least one controller, at least two PCIE 10 modules, and at least two storage devices, where the at least two storage devices pass through the at least one controller.
  • the PCIE switch chip is connected, and the at least two PCIE 10 modules are connected by the PCIE switch chip of the at least one controller, where the controller includes:
  • a receiving module configured to receive a request message from the server by using at least two PCIE 10 modules; and an access module, configured to access the at least two storage devices according to the request message.
  • the embodiment of the invention has the following advantages:
  • the controllers By connecting at least two PCIE 10 modules by using the controller's PCIE switch chip, the controllers share at least two PCIE 10 modules, saving resources; and at least two storage devices by using the controller's PCIE switch chip Connection, the storage device does not need to expand the chip through the hard disk controller and the hard disk when accessing the controller, thereby saving cost.
  • FIG. 2 is a flowchart of a storage method according to Embodiment 2 of the present invention.
  • FIG. 3 is a structural diagram of a storage architecture based on a PCIE interconnection according to Embodiment 2 of the present invention
  • FIG. 4 is a structural diagram of a storage system according to Embodiment 3 of the present invention
  • FIG. 5 is a structural diagram of a storage device according to Embodiment 4 of the present invention. detailed description
  • Embodiment 1 is a flowchart of a storage method according to Embodiment 1 of the present invention, which may be applied to a system including at least one controller, at least two PCIE 10 modules, and at least two storage devices, where the at least two storage devices pass
  • the PCIE switch chip of the at least one controller is connected, and the at least two PCIE 10 modules are connected by the PCIE switch chip of the at least one controller.
  • the method may include:
  • Step S101 Receive a request message from the server by using the at least two PCIE 10 modules.
  • Step S102 Access the at least two storage devices according to the request message.
  • the method of the embodiment of the present invention can adjust the sequence of each step according to actual needs.
  • the storage device of the embodiment of the present invention may be a solid state hard disk.
  • the body that receives the request message from the server through the at least two PCIE 10 modules may be the server with the lightest load, and the lightest controller. It includes at least one of the following: The controller has the least number of requests; the controller has the shortest response time; the controller has the lowest CPU usage.
  • At least two PCIE 10 modules are connected by using a PCIE switch chip of the controller, so that at least two PCIE 10 modules are shared between the controllers, thereby saving resources; and the PCIE switch chip by using the controller
  • At least two storage devices are connected, and a solid-state hard disk is used as a storage device instead of a conventional hard disk, so that the solid-state hard disk does not need to expand the chip through the hard disk controller and the hard disk when accessing the controller, thereby saving cost.
  • the server can select the controller with the lightest load according to the load condition of the controller, thereby achieving the dynamic balance of the controller load.
  • Step S201 The server sends a request to the controller with the lightest load.
  • the server can send the request to the lightest load controller through the multipath software
  • the multipath software is software that can automatically select the path, that is, the server multipath software can interact with the controller to automatically select the lightest load.
  • the controller sends the request to the lightest controller of the load, including but not limited to a request to perform a storage operation through the home controller.
  • the lightest load controllers described above include, but are not limited to, the minimum number of requests from the controller, the shortest response time of the controller, and the lowest CPU usage.
  • the foregoing controller may be a controller based on a PCIE interconnected storage architecture
  • FIG. 3 is a structural diagram of a PCIE interconnect-based storage architecture according to Embodiment 2 of the present invention, as shown in FIG.
  • the storage architecture is illustrated by taking two controllers as an example.
  • an input and output module (PCIE 10) PCIE 10
  • a PCIE switch chip PCIE switch chip
  • a controller PCIE a storage device
  • the storage device may be a hard disk, and the types of the hard disk include but are not limited to a solid state hard disk (Solid State Di sk, Abbreviation: SSD).
  • SSD Solid State Di sk
  • the storage device is described by using a solid state disk as an example.
  • the controller can be configured with multiple PCIE 10 modules.
  • the SSD is taken as an example for description.
  • the PCIE 10 module, the PCIE switch chip, the controller, and the PCIE SSD are all described by taking two examples.
  • the above PCIE 10 module is used.
  • the number of PCIE switch chips, controllers, and PCIE SSDs can be arbitrarily selected according to actual needs.
  • the above two controllers are the controller 33 and the controller 34.
  • the above two PCIE 10 modules are the PCIE 10 module 321 and the PCIE 10 module 322.
  • the above two PCIE switch chips are located in the controller, and the PCIE switch chip 331 is located. Within the controller 33, the PCIE switch chip 341 is located in the controller 34.
  • the two PCIE SSDs described above are the PCIE SSD 351 and the PCIE SSD 352.
  • the PCIE 10 module 322 is connected to the PCIE switch chip 341, so that the PCIE 10 module 321 and the PCIE 10 module 322 are in two.
  • the controllers are interconnected, so that the controller 33 and the controller 34 can share the PCIE 10 module 321 and the PCIE 10 module 322, and the PCIE SSD 351 is also connected to the PCIE switch chip 331, and the PCIE SSD 352 is also connected to the PCIE switch chip 341.
  • the PCIE SSD 351 and the PCIE SSD 352 are interconnected, so that the controller 33 and the controller 34 can access all the PCIE SSDs, that is, the controller 33 and the controller 34 can share the access PCIE SSD 351 and store the information.
  • the controller 33 and controller 34 can also share access to the PCIE SSD 352 and store the information on the PCIE SSD 352.
  • the request from the server received by the controller in the storage architecture 3 is specifically a request sent by the server 311 through the switching network, and the request received by the controller in the storage architecture 3 from the server may also be passed by the server 312.
  • the lightest load controller stores the information corresponding to the request on the PCIE SSD by accessing the PCIE SSD.
  • the controller 33 can store the network information on the PCIE SSD 351, and can also store the network information on the PCIE SSD 352.
  • the method of the embodiment of the present invention can adjust the sequence of each step according to actual needs.
  • the PCIE 10 module is interconnected between the two controllers by using the PCIE switch chip, so that the two controllers can share all the PCIE 10 modules, which saves the resources of the PCIE interface card.
  • the SSD can directly access the controller, and does not need to access the controller through the hard disk controller and the hard disk expansion chip, thereby saving the high cost of using the hard disk controller and the hard disk expansion chip, and using the traditional hard disk access controller
  • the access paths are: CPU, PCIE bus bridge, PCIE bus, hard disk controller, hard disk expansion chip, and hard disk.
  • the traditional interface includes but is not limited to Fibre Channel (Fibre Channe l, Abbreviation: FC) and Serial SCSI ( Ser ia tached SCSI, SAS for short).
  • Fibre Channel Fibre Channe l, Abbreviation: FC
  • Serial SCSI Ser ia tached SCSI, SAS for short.
  • the CPU instruction execution time is ns level
  • the memory access delay is 10 ns
  • the disk access time is more than a dozen.
  • the storage device of the system by using a high-performance, non-volatile SSD as the storage device of the system, it is not necessary to design a home controller on the LUN of the Cache, and the request for a certain LUN can be executed on any controller. , that is, the LUN can access the SSD through any controller.
  • the controller's PCIE switch chip to connect the two SSDs, the path between the server multipath software and the controller is peer-to-peer, and there is no longer a preferred path between the controllers.
  • the server multipath software can pass.
  • the load condition of the controller selects the requested path to achieve the dynamic balance of the controller load.
  • the system may include: at least one controller, at least two PCIE 10 modules, and at least two storage devices, the at least two The storage device is connected by a PCIE switch chip of the at least one controller, and the at least two PCIE 10 modules are connected by a PCIE switch chip of the at least one controller, and one controller can be configured with multiple PCIE 10 modules.
  • the at least one controller, the at least two PCIE 10 modules, and the at least two storage devices are respectively illustrated by using two examples, that is, the storage system.
  • the system includes: a controller 41, a controller 42, a PCIE 10 module 43, a PCIE 10 module 44, a storage device 45, and a storage device 46.
  • the controller 41 includes a PCIE switch chip 411
  • the controller 42 includes a PCIE switch chip 421.
  • the PCIE switch chip 411 is connected to the PCIE switch chip 421
  • the PCIE 10 module 43 is connected to the PCIE switch chip 411
  • the PCIE 10 module 44 is connected to the PCIE switch chip 421
  • the storage device 45 is connected to the PCIE switch chip 411
  • the storage device 46 and the PCIE switch are connected.
  • the chip 421 is connected.
  • the controller 41 is configured to receive a request message from the server through the PCIE 10 module 43.
  • the controller 41 is further configured to receive a request message from the server through the PCIE 10 module 44, and the controller 41 accesses the storage device 45 according to the request message.
  • the controller 41 can also access the storage device 46 according to the request message, where the type of the storage device includes, but is not limited to, a solid state hard disk; the storage device is configured to store information that needs to be stored corresponding to the request message.
  • the controller 41 is the controller with the lightest load.
  • the various units of the system of the embodiments of the present invention may be integrated into one device or may be distributed to multiple devices. The above units may be combined into one unit, or may be further split into a plurality of subunits.
  • At least two PC IE 10 modules are connected by using a PC IE switch chip of the controller, so that at least two PCIE 10 modules are shared between the controllers, saving resources; PCIE exchange by using a controller
  • the chip connects at least two storage devices and uses a solid-state hard disk as a storage device to replace the traditional hard disk, so that the solid-state hard disk does not need to expand the chip through the hard disk controller and the hard disk when accessing the controller, thereby saving cost.
  • the server can select the controller with the lightest load according to the load condition of the controller, thereby achieving the dynamic balance of the controller load.
  • FIG. 5 is a structural diagram of a storage device according to Embodiment 4 of the present invention, where the device may be a controller, where the controller is applied to include at least one controller, at least two PCIE 10 modules, and at least In a system of two storage devices, the at least two storage devices are connected by a PCIE switch chip of the at least one controller, and the at least two PCIE 10 modules are connected by a PCIE switch chip of the at least one controller, wherein the controller
  • the controller that can be the lightest load as shown in Figure 5, can include:
  • connection module 51 is configured to connect the PCIE switch chip in the at least one controller to connect at least two storage devices, including but not limited to a solid state drive;
  • the PCIE switch chip in the at least one controller is connected to connect the at least two PCIE 10 modules.
  • the receiving module 52 is configured to receive a request message from the server by using at least two PCIE 10 modules.
  • the access module 53 is configured to access at least two storage devices connected by the connection module 51 according to the request message received by the receiving module 52.
  • the storage module 54 is configured to store information corresponding to the request message received by the receiving module 52 into the at least two storage devices when the access module 53 accesses the storage device, and the type of the storage device includes, but is not limited to, a solid state hard disk.
  • the modules of the device in the embodiment of the present invention may be integrated into one module, or may be separately deployed.
  • the above modules can be combined into one module, or they can be further split into multiple sub-modules.
  • At least two PC IE 10 modules are connected by using a PC IE switch chip of the controller, so that at least two PCIE 10 modules are shared between the controllers, saving resources; PCIE exchange by using a controller
  • the chip connects at least two storage devices and uses a solid-state hard disk as a storage device to replace the traditional hard disk, so that the solid state hard disk does not need to pass through when accessing the controller.
  • the hard disk controller and the hard disk expansion chip save cost.
  • the server can select the controller with the lightest load according to the load condition of the controller, thereby achieving the dynamic balance of the controller load.
  • the present invention can be implemented by hardware, or can be implemented by means of software plus a necessary general hardware platform.
  • the technical solution of the present invention may be embodied in the form of a software product, which may be stored in a non-volatile storage medium (which may be a CD-ROM, a USB flash drive, a mobile hard disk, etc.), including several The instructions are for causing a computer device (which may be a personal computer, server, or network device, etc.) to perform the methods described in various embodiments of the present invention.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
  • Information Transfer Systems (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Description

一种存储方法、 存储系统及控制器 技术领域
本发明涉及信息技术领域,特别是涉及一种存储方法、存储系统及控制器。
背景技术
随着科学技术的飞速发展以及计算机技术的普遍应用, 互联网上信息迅 速增加, 而且电子商务不断发展, 企业的信息系统日益占据着企业竟争的主 体地位, 使得数据量的增长很快, 企业越来越依赖于数据。 为了更好、 更快 的存储大量的数据, 存储技术也需要不断的发展。
现有技术中, 为了简化高速緩冲存储器(Cache) 的设计, 需要在 Cache 的逻辑单元(Logical Unit Number, 简称: LUN )上设计归属控制器, 从而 使得针对某个 LUN的请求在归属控制器上执行。控制器 -0和控制器 -1通过镜 像通道相连接,镜像通道分别与控制器 -0的镜像芯片和控制器 -1的镜像芯片 相连接,服务器通过交换网分别与控制器 -0的外设组件互连标准( Peripheral Component Interconnection Express , 简称: PCIE )接口卡和控制器_1 的 PCIE接口卡相连接, 而控制器 -0 通过硬盘扩展芯片与传统接口的硬盘相连 接, 控制器 -1也通过硬盘扩展芯片与传统接口的硬盘相连接, 在控制器内, 硬盘扩展芯片通过硬盘控制器与 PCIE交换芯片 (Switch)连接, PCIE 交换 芯片分别与 PCIE接口卡、镜像芯片和硬盘控制器连接, 并通过中央处理单元 (Central Processing Unit, 简称: CPU)和芯片组与内存相连接。 当服务器发送请求时, 通过优选(最近)路径将请求发送给控制器, 并 判断该控制器是否在归属控制器, 当该控制器是归属控制器时, 由该控制器 处理该请求; 当该控制器不是归属控制器时, 转发给归属控制器, 使得归属 控制器处理该请求。 例如, LUN_ 0 的归属控制器是控制器 - 0, 当服务器通过 优选路径 PCIE接口卡 n将针对 LUN - 0的请求发送给控制器 _ 1时, 当判断出 控制器 - 1不是 LUN_ 0的归属控制器时, 将针对 LUN_ 0的请求转发给 LUN_ 0的 归属控制器, 即将针对 LUN_ 0的请求通过镜像通道转发给控制器 _ 0, 由控制 器 - 0对该请求进行处理。 在实现本发明的过程中, 发明人发现现有技术中至少存在如下问题: 控制器 - 0和控制器 - 1具有独立的 PCIE接口卡, 但不能被对端控制器使 用, 造成资源的浪费, 而且传统硬盘须通过硬盘控制器和硬盘扩展芯片才能 接入存储控制器 , 而使用硬盘控制器和硬盘扩展芯片造成控制器成本较高。 发明内容
本发明实施例提供一种存储方法、 存储系统及控制器, 以使控制器之间 共享存储设备和 PCIE 10模块。 为了达到上述目的, 本发明实施例提出了一种存储方法, 应用于包括至 少一个控制器、 至少两个外设组件互连标准 PCIE 输入输出 10模块以及至少 两个存储设备的系统中, 所述至少两个存储设备通过所述至少一个控制器的 PCIE交换芯片连接,所述至少两个外设组件互连标准 PCIE 输入输出 10模块 通过所述至少一个控制器的 PCIE交换芯片连接, 所述方法包括:
通过所述至少两个外设组件互连标准 PCIE 输入输出 10模块接收来自服 务器的请求消息; 根据所述请求消息访问所述至少两个存储设备。 本发明实施例提出了一种存储系统, 包括: 至少一个控制器、 至少两个 PCIE 10 模块以及至少两个存储设备, 所述至少两个存储设备通过所述至少 一个控制器的 PCIE交换芯片连接, 所述至少两个 PCIE 10模块通过所述至少 一个控制器的 PCIE交换芯片连接, 其中:
控制器, 用于通过所述至少两个 PCIE 10模块接收来自服务器的请求消 息, 根据所述请求消息访问所述至少两个存储设备;
所述至少两个存储设备, 用于存储所述请求消息对应的信息。
本发明实施例提出了一种控制器, 应用于包括至少一个控制器、 至少两 个 PCIE 10模块以及至少两个存储设备的系统中, 所述至少两个存储设备通 过所述至少一个控制器的 PCIE交换芯片连接, 所述至少两个 PCIE 10模块通 过所述至少一个控制器的 PCIE交换芯片连接, 其中, 控制器包括:
接收模块, 用于通过至少两个 PCIE 10模块接收来自服务器的请求消息; 访问模块, 用于根据所述请求消息访问至少两个存储设备。
与现有技术相比, 本发明实施例具有以下优点:
通过使用控制器的 PCIE交换芯片将至少两个 PCIE 10模块连接, 使得控 制器之间共享至少两个 PCIE 10模块, 节省了资源; 而且通过使用控制器的 PCIE交换芯片将至少两个存储设备相连接, 存储设备在接入控制器时并不需 要通过硬盘控制器和硬盘扩展芯片, 从而节省了成本。 附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案, 下面将对实 施例或现有技术描述中所需要使用的附图作简单地介绍, 显而易见地, 下面 描述中的附图仅仅是本发明的一些实施例, 对于本领域普通技术人员来讲, 在不付出创造性劳动性的前提下, 还可以根据这些附图获得其他的附图。 图 1为本发明实施例一提出的一种存储方法流程图;
图 2为本发明实施例二提出的一种存储方法流程图;
图 3为本发明实施例二提出的一种基于 PCIE互联的存储架构的结构图; 图 4为本发明实施例三提出的一种存储系统结构图;
图 5为本发明实施例四提出的一种存储装置结构图。 具体实施方式
下面将结合本发明实施例中的附图, 对本发明实施例中的技术方案进行 清楚、 完整地描述, 显然, 所描述的实施例仅仅是本发明一部分实施例, 而 不是全部的实施例。 基于本发明中的实施例, 本领域普通技术人员在没有作 出创造性劳动前提下所获得的所有其他实施例 , 都属于本发明保护的范围。
图 1为本发明实施例一提出的一种存储方法流程图, 可以应用于包括至 少一个控制器、 至少两个 PCIE 10模块以及至少两个存储设备的系统中, 所 述至少两个存储设备通过所述至少一个控制器的 PCIE交换芯片连接,所述至 少两个 PCIE 10模块通过所述至少一个控制器的 PCIE交换芯片连接, 如图 1 所示, 可以包括:
步骤 S101 ,通过所述至少两个 PCIE 10模块接收来自服务器的请求消息; 步骤 S102 , 根据所述请求消息访问所述至少两个存储设备。
本发明实施例方法可以根据实际需要对各个步骤顺序进行调整。
本发明实施例的存储设备可以是固态硬盘, 本实施例中, 该通过所述至 少两个 PCIE 10模块接收来自服务器的请求消息的主体可以为负载最轻的服 务器, 该负载最轻的控制器包括以下中的至少一种: 控制器的请求数量最少; 控制器响应时间最短; 控制器的 CPU占用率最小。 可见,本实施例中,通过使用控制器的 PCIE交换芯片将至少两个 PCIE 10 模块连接, 使得控制器之间共享至少两个 PCIE 10模块, 节省了资源; 通过 使用控制器的 PCIE交换芯片将至少两个存储设备相连接,并使用固态硬盘作 为存储设备, 替代传统的硬盘, 使得固态硬盘在接入控制器时并不需要通过 硬盘控制器和硬盘扩展芯片, 从而节省了成本。 而且在将固态硬盘连接后使 服务器可以根据控制器的负载情况选择负载最轻的控制器, 从而达到控制器 负载的动态平衡。
图 2为本发明实施例二提出的一种存储方法流程图, 如图 2所示, 可以 包括:
步骤 S201 , 服务器向负载最轻的控制器发送请求。
具体的, 服务器可以通过多路径软件将请求发送给负载最轻的控制器, 该多路径软件为可以自动选路的软件, 即服务器的多路径软件可以通过和控 制器交互, 自动选择负载最轻的控制器, 并将请求发送给该负载最轻的控制 器, 该请求包括但不限于通过归属控制器进行存储操作的请求。 上述的负载 最轻的控制器包括但不限于控制器的请求数量最少、 控制器响应时间最短、 CPU占用率最小。
本实施例中, 上述的控制器可以为基于 PCIE互联存储架构中的控制器, 其中,图 3为本发明实施例二提出的一种基于 PCIE互联的存储架构的结构图, 如图 3所示, 该存储架构以两个控制器为例进行说明。 在该存储架构 3中, 包括输入输出模块( PCIE 10 ) 、 PCIE交换芯片、 控制器和存储设备, 该存 储设备可以为硬盘,该硬盘的类型包括但不限于固态硬盘(Sol id State Di sk, 简称: SSD ) , 本实施例中, 该存储设备均以固态硬盘为例进行说明, 一个控 制器可以配置多个 PCIE 10模块。 在本实施例中, 以 SSD为例进行说明, 上 述的 PCIE 10模块、 PCIE 交换芯片、 控制器和 PCIE SSD均以两个为例进行 说明, 在使用该存储架构 3时, 上述的 PCIE 10模块、 PCIE 交换芯片、 控制 器和 PCIE SSD 的个数根据实际需要任意选取。 上述的两个控制器为控制器 33和控制器 34 , 上述的两个 PCIE 10模块为 PCIE 10模块 321和 PCIE 10模 块 322 , 上述的两个 PCIE 交换芯片位于控制器内, PCIE 交换芯片 331位于 控制器 33内, PCIE 交换芯片 341位于控制器 34内, 上述的两个 PCIE SSD 为 PCIE SSD 351和 PCIE SSD 352。
通过将 PCIE 交换芯片 331和 PCIE 交换芯片 341连接, 并将 PCIE 10模 块 321与 PCIE 交换芯片 331连接, 将 PCIE 10模块 322与 PCIE 交换芯片 341连接, 使得 PCIE 10模块 321与 PCIE 10模块 322在两个控制器之间互 联, 从而控制器 33和控制器 34可以共享 PCIE 10模块 321与 PCIE 10模块 322 , 而且 PCIE SSD 351也与 PCIE 交换芯片 331连接, PCIE SSD 352也与 PCIE 交换芯片 341连接, 使得 PCIE SSD 351与 PCIE SSD 352两个控制器之 间互联, 从而控制器 33和控制器 34可以访问所有的 PCIE SSD, 即控制器 33 和控制器 34可以共享访问 PCIE SSD 351 , 并将信息存储到 PCIE SSD 351上, 同样的, 控制器 33和控制器 34还可以共享访问 PCIE SSD 352 , 并将信息存 储到 PCIE SSD 352上。
本实施例中, 该存储架构 3中的控制器接收的来自服务器的请求具体为 服务器 311通过交换网发送的请求, 该存储架构 3中的控制器接收的来自服 务器的请求还可以为服务器 312通过交换网发送的请求, 其中, 该控制器为 负载最轻的控制器。 步骤 S202 , 控制器处理来自服务器的请求。
具体的, 当该来自服务器的请求为存储操作的请求时, 该负载最轻的控 制器通过访问 PCIE SSD, 将该请求所对应的信息存储到该 PCIE SSD上。 例 如,当该服务器的请求为存储网络信息,该负载最轻的控制器为控制器 33时, 在控制器 33接收到该来自服务器的存储网络信息的请求后,将该请求所对应 的网络信息存储到 PCIE SSD中, 本实施例中, 控制器 33可以将该网络信息 存储到 PCIE SSD 351上, 也可以将该网络信息存储到 PCIE SSD 352上。
本发明实施例方法可以根据实际需要对各个步骤顺序进行调整。
可见, 本实施例中, 通过使用 PCIE 交换芯片将 PCIE 10模块在两个控 制器之间互联, 使得两个控制器可以共享所有的 PCIE 10模块, 节省了 PCIE 接口卡的资源。
并且 SSD可以直接接入控制器, 并不需要通过硬盘控制器、 硬盘扩展芯 片接入控制器, 从而节省了使用硬盘控制器、 硬盘扩展芯片的高成本, 而在 使用传统硬盘接入控制器, CPU 在访问传统接口的硬盘时, 其访问路径依次 为: CPU、 PCIE总线的桥片、 PCIE总线、 硬盘控制器、 硬盘扩展芯片、 硬盘, 该传统接口包括但不限于光纤通道(Fibre Channe l , 简称: FC )和串行 SCSI ( Ser ia l At tached SCSI , 简称: SAS ) , 在访问时间上, CPU指令的执行时 间是 ns级, 内存访问延迟是 10ns级, 而磁盘访问时间为十几个毫秒级, 当 存储设备的访问延迟需要大大提高后, 例如, 当存储设备的访问延迟需要提 高到 0. lms时, 上述的通过 CPU、 PCIE总线的桥片、 PCIE总线、硬盘控制器、 硬盘扩展芯片、 硬盘的访问路径将在性能上将存在瓶颈, 通过上述的访问路 径不能使存储设备的访问延迟达到 0. 1ms , 当仍使用传统接口的硬盘时, 便 不能满足性能要求了, 此时, 需要存储介质在总线层次上更接近 CPU和内存, 即使用 SSD直接接入控制器。 通过表 1和表 2可以看出,基于 PCIE接口的固 态硬盘性能指标远远高于机械硬盘性能指标, 其中, 表 1为基于 PCIE接口的 固态硬盘性能指标, 表 2为机械硬盘性能指标。
表 1
Figure imgf000010_0001
即在本实施例中, 通过使用高性能、 非易失性的 SSD作为系统的存储设 备, 不需要在 Cache的 LUN上设计归属控制器, 针对某个 LUN的请求可以在 任意的控制器上执行, 即 LUN可通过任意控制器访问 SSD。 此时, 通过使用 控制器的 PCIE 交换芯片将两个 SSD相连接, 服务器多路径软件和控制器间 的路径为对等关系, 控制器之间不再有优选路径, 服务器多路径软件就可以 通过控制器的负荷情况选择请求的路径, 以达到控制器负载的动态平衡。
图 4为本发明实施例三提出的一种存储系统结构图, 如图 4所示, 该系 统可以包括: 至少一个控制器、 至少两个 PCIE 10模块以及至少两个存储设 备, 该至少两个存储设备通过该至少一个控制器的 PCIE 交换芯片连接, 该 至少两个 PCIE 10模块通过该至少一个控制器的 PCIE 交换芯片连接, 一个 控制器可以配置多个 PCIE 10模块。 本实施例中, 该至少一个控制器、 至少 两个 PCIE 10模块、 至少两个存储设备均以两个为例进行说明, 即该存储系 统包括: 控制器 41、 控制器 42、 PCIE 10模块 43、 PCIE 10模块 44、 存储设 备 45、 存储设备 46; 该控制器 41中包括 PCIE 交换芯片 411 , 该控制器 42 中包括 PCIE 交换芯片 421 , PCIE 交换芯片 411和 PCIE 交换芯片 421连接, PCIE 10模块 43和 PCIE 交换芯片 411连接, PCIE 10模块 44和 PCIE 交换 芯片 421连接,存储设备 45和 PCIE 交换芯片 411连接,存储设备 46和 PCIE 交换芯片 421连接。 其中, 控制器 41用于通过 PCIE 10模块 43接收来自服 务器的请求消息, 此外, 控制器 41还用于通过 PCIE 10模块 44接收来自服 务器的请求消息, 控制器 41根据该请求消息访问存储设备 45 , 同样的, 控 制器 41还可以根据该请求消息访问存储设备 46 , 其中, 存储设备的类型包 括但不限于固态硬盘; 该存储设备用于存储该请求消息对应的需要存储的信 息。 本实施例中, 控制器 41为负载最轻的控制器。 本发明实施例系统的各个 单元可以集成于一个装置, 也可以分布于多个装置。 上述单元可以合并为一 个单元, 也可以进一步拆分成多个子单元。
可见,本实施例中,通过使用控制器的 PC I E 交换芯片将至少两个 PC I E 10 模块连接, 使得控制器之间共享至少两个 PCIE 10模块, 节省了资源; 通过 使用控制器的 PCIE 交换芯片将至少两个存储设备相连接, 并使用固态硬盘 作为存储设备, 替代传统的硬盘, 使得固态硬盘在接入控制器时并不需要通 过硬盘控制器和硬盘扩展芯片, 从而节省了成本。 而且在将固态硬盘连接后 使服务器可以根据控制器的负载情况选择负载最轻的控制器, 从而达到控制 器负载的动态平衡。
图 5为本发明实施例四提出的一种存储装置结构图, 该装置可以为控制 器, 该控制器应用于包括至少一个控制器、 至少两个 PCIE 10模块以及至少 两个存储设备的系统中, 该至少两个存储设备通过该至少一个控制器的 PCIE 交换芯片连接, 该至少两个 PCIE 10模块通过该至少一个控制器的 PCIE 交 换芯片连接, 其中, 该控制器可以为负载最轻的控制器, 如图 5所示, 可以 包括:
连接模块 51 , 用于将至少一个控制器中的 PCIE 交换芯片连接, 以使至 少两个存储设备相连接, 存储设备的类型包括但不限于固态硬盘;
或者,
用于将该至少一个控制器中的 PCIE 交换芯片连接, 以使该至少两个 PCIE 10模块相连接。
接收模块 52 , 用于通过至少两个 PCIE 10模块接收来自服务器的请求消 息。
访问模块 53 , 用于根据接收模块 52接收的请求消息访问连接模块 51连 接的至少两个存储设备。
存储模块 54 , 用于在访问模块 53访问存储设备时, 将接收模块 52接收 的请求消息对应的信息存储到该至少两个存储设备中, 该存储设备的类型包 括但不限于固态硬盘。
本发明实施例设备的各个模块可以集成于一体, 也可以分离部署。 上述 模块可以合并为一个模块, 也可以进一步拆分成多个子模块。
可见,本实施例中,通过使用控制器的 PC I E 交换芯片将至少两个 PC I E 10 模块连接, 使得控制器之间共享至少两个 PCIE 10模块, 节省了资源; 通过 使用控制器的 PCIE 交换芯片将至少两个存储设备相连接, 并使用固态硬盘 作为存储设备, 替代传统的硬盘, 使得固态硬盘在接入控制器时并不需要通 过硬盘控制器和硬盘扩展芯片, 从而节省了成本。 而且在将固态硬盘连接后 使服务器可以根据控制器的负载情况选择负载最轻的控制器, 从而达到控制 器负载的动态平衡。
通过以上的实施方式的描述, 本领域的技术人员可以清楚地了解到本发 明可以通过硬件实现, 也可以可借助软件加必要的通用硬件平台的方式来实 现。 基于这样的理解, 本发明的技术方案可以以软件产品的形式体现出来, 该软件产品可以存储在一个非易失性存储介质 (可以是 CD-ROM, U盘, 移动 硬盘等) 中, 包括若干指令用以使得一台计算机设备(可以是个人计算机, 服务器, 或者网络设备等)执行本发明各个实施例所述的方法。
以上所述仅是本发明的优选实施方式, 应当指出, 对于本技术领域的普 通技术人员来说, 在不脱离本发明原理的前提下, 还可以做出若干改进和润 饰, 这些改进和润饰也应视本发明的保护范围。

Claims

权 利 要 求
1、 一种存储方法, 其特征在于, 应用于包括至少一个控制器、 至少两个 外设组件互连标准 PCIE 输入输出 10模块以及至少两个存储设备的系统中, 所述至少两个存储设备通过所述至少一个控制器的 PCIE交换芯片连接,所述 至少两个外设组件互连标准 PCIE 输入输出 10模块通过所述至少一个控制器 的 PCIE交换芯片连接, 所述方法包括:
通过所述至少两个外设组件互连标准 PCIE 输入输出 10模块接收来自服 务器的请求消息;
根据所述请求消息访问所述至少两个存储设备。
2、 如权利要求 1所述的存储方法, 其特征在于, 所述根据所述请求消息 访问所述至少两个存储设备包括:
将所述请求消息对应的信息存储到所述至少两个存储设备中。
3、 如权利要求 1所述的存储方法, 其特征在于, 所述至少两个存储设备 通过所述至少一个控制器的 PCIE交换芯片连接包括:
通过将所述至少一个控制器中的 PCIE交换芯片连接,以使所述至少两个 存储设备相连接;
或者,
所述至少两个外设组件互连标准 PCIE 输入输出 10模块通过所述至少一 个控制器的 PCIE交换芯片连接包括:
通过将所述至少一个控制器中的 PCIE交换芯片连接,以使所述至少两个 外设组件互连标准 PCIE 输入输出 10模块相连接。
4、 如权利要求 1所述的存储方法, 其特征在于, 所述至少一个控制器中 包括负载最轻的控制器, 所述负载最轻的控制器通过所述至少两个外设组件 互连标准 PCIE 输入输出 10模块接收所述来自服务器的请求消息。
5、 如权利要求 4所述的存储方法, 其特征在于, 所述负载最轻的控制器 包括以下中的至少一种:
控制器的请求数量最少;控制器响应时间最短;控制器的 CPU占用率最小。
6、 如权利要求 1至 5任一项所述的存储方法, 其特征在于, 所述存储设 备的类型包括固态硬盘。
7、 一种存储系统, 其特征在于, 包括: 至少一个控制器、 至少两个 PCIE 10模块以及至少两个存储设备, 所述至少两个存储设备通过所述至少一个控 制器的 PCIE交换芯片连接, 所述至少两个 PCIE 10模块通过所述至少一个控 制器的 PCIE交换芯片连接, 其中:
控制器, 用于通过所述至少两个 PCIE 10模块接收来自服务器的请求消 息, 根据所述请求消息访问所述至少两个存储设备;
所述至少两个存储设备, 用于存储所述请求消息对应的信息。
8、 如权利要求 7所述的存储系统, 其特征在于, 所述存储设备的类型包 括固态硬盘。
9、 一种控制器, 其特征在于, 应用于包括至少一个控制器、 至少两个 PCIE 10 模块以及至少两个存储设备的系统中, 所述至少两个存储设备通过 所述至少一个控制器的 PCIE交换芯片连接, 所述至少两个 PCIE 10模块通过 所述至少一个控制器的 PCIE交换芯片连接, 其中, 控制器包括:
接收模块, 用于通过至少两个 PCIE 10模块接收来自服务器的请求消息; 访问模块, 用于根据所述请求消息访问至少两个存储设备。
10、 如权利要求 9所述的控制器, 其特征在于, 还包括: 存储模块, 用于将所述请求消息对应的信息存储到所述至少两个存储设 备中。
11、 如权利要求 10所述的控制器, 其特征在于, 还包括:
连接模块, 用于将所述至少一个控制器中的 PCIE交换芯片连接, 以使所 述至少两个存储设备相连接;
或者,
用于将所述至少一个控制器中的 PCIE交换芯片连接,以使所述至少两个 PCIE 10模块相连接。
12、 如权利要求 9至 11任一项所述的控制器, 其特征在于, 所述存储设 备的类型包括固态硬盘。
PCT/CN2009/075168 2008-12-24 2009-11-27 一种存储方法、存储系统及控制器 WO2010072113A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP09834066A EP2378430A4 (en) 2008-12-24 2009-11-27 STORAGE METHOD, STORAGE SYSTEM, AND CONTROLLER
US13/168,552 US8296476B2 (en) 2008-12-24 2011-06-24 Storage method, storage system, and controller

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN2008101875170A CN101763221B (zh) 2008-12-24 2008-12-24 一种存储方法、存储系统及控制器
CN200810187517.0 2008-12-24

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US13/168,552 Continuation US8296476B2 (en) 2008-12-24 2011-06-24 Storage method, storage system, and controller

Publications (1)

Publication Number Publication Date
WO2010072113A1 true WO2010072113A1 (zh) 2010-07-01

Family

ID=42286889

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2009/075168 WO2010072113A1 (zh) 2008-12-24 2009-11-27 一种存储方法、存储系统及控制器

Country Status (4)

Country Link
US (1) US8296476B2 (zh)
EP (1) EP2378430A4 (zh)
CN (1) CN101763221B (zh)
WO (1) WO2010072113A1 (zh)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102043592B (zh) * 2010-12-09 2012-05-02 成都市华为赛门铁克科技有限公司 固态硬盘的连接处理方法、装置和系统
US9767058B2 (en) * 2011-11-17 2017-09-19 Futurewei Technologies, Inc. Method and apparatus for scalable low latency solid state drive interface
US20130290594A1 (en) * 2011-12-21 2013-10-31 Timothy J. Callahan Core-driven translation and loopback test
US9619628B2 (en) * 2012-09-28 2017-04-11 Intel Corporation Secure system flash sharing
EP2811413B1 (en) 2013-05-02 2016-10-19 Huawei Technologies Co., Ltd. Computer system, access method and apparatus for peripheral component interconnect express endpoint device
CN103488436B (zh) * 2013-09-25 2017-04-26 华为技术有限公司 内存扩展系统及方法
CN104038548A (zh) * 2014-06-18 2014-09-10 英业达科技有限公司 服务器系统
CN105472291B (zh) * 2014-09-12 2019-01-08 杭州海康威视数字技术股份有限公司 多处理器集群的数字硬盘录像机及其实现方法
BR112016003843B1 (pt) * 2014-09-15 2019-04-24 Huawei Technologies Co., Ltd. Método de processamento de solicitação de gravar dados e arranjo de armazenamento
US10162786B2 (en) * 2014-12-01 2018-12-25 SK Hynix Inc. Storage node based on PCI express interface
WO2016101287A1 (zh) 2014-12-27 2016-06-30 华为技术有限公司 一种存储系统数据分发的方法、分发装置与存储系统
CN104639469A (zh) * 2015-02-06 2015-05-20 方一信息科技(上海)有限公司 一种基于pcie互连的计算和存储集群系统
US9841904B2 (en) 2015-03-02 2017-12-12 Samsung Electronics Co., Ltd. Scalable and configurable non-volatile memory module array
US10437747B2 (en) * 2015-04-10 2019-10-08 Rambus Inc. Memory appliance couplings and operations
CN105607872A (zh) * 2015-12-17 2016-05-25 山东海量信息技术研究院 一种存储装置
CN107291370B (zh) * 2016-03-30 2021-06-04 杭州海康威视数字技术股份有限公司 一种云存储系统调度方法和装置
US10445280B2 (en) * 2016-10-12 2019-10-15 Lenovo Enterprise Solutions (Singapore) Pte. Ltd. PCIe switch for aggregating a large number of endpoint devices
CN108121496B (zh) * 2016-11-28 2021-01-29 成都华为技术有限公司 数据的存储方法、装置和系统
ES2800064T3 (es) 2016-12-28 2020-12-23 Huawei Tech Co Ltd Procedimiento, dispositivo y sistema para transferencia de paquetes en NVME sobre tejido
CN108009109A (zh) * 2017-11-30 2018-05-08 郑州云海信息技术有限公司 一种基于U.2接口支持自Raid功能的PCIE存储装置
US11194746B2 (en) 2017-12-22 2021-12-07 Seagate Technology Llc Exchanging drive information
CN109408440A (zh) * 2018-11-06 2019-03-01 郑州云海信息技术有限公司 一种pcie扩展装置
US11132326B1 (en) * 2020-03-11 2021-09-28 Nvidia Corporation Techniques to transfer data among hardware devices
CN112000286B (zh) * 2020-08-13 2023-02-28 北京浪潮数据技术有限公司 一种四控全闪存储系统及其故障处理方法、装置
US20230171099A1 (en) * 2021-11-27 2023-06-01 Oracle International Corporation Methods, systems, and computer readable media for sharing key identification and public certificate data for access token verification

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1821946A (zh) * 2006-02-16 2006-08-23 杭州华为三康技术有限公司 一种存储系统以及存储数据的方法和读取数据的方法
US20070098001A1 (en) * 2005-10-04 2007-05-03 Mammen Thomas PCI express to PCI express based low latency interconnect scheme for clustering systems
CN101149664A (zh) * 2007-10-26 2008-03-26 华为技术有限公司 固态硬盘及处理其管理数据的方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6757778B1 (en) 2002-05-07 2004-06-29 Veritas Operating Corporation Storage management system
US8301809B2 (en) * 2003-07-02 2012-10-30 Infortrend Technology, Inc. Storage virtualization computer system and external controller thereof
CN1254748C (zh) 2003-10-31 2006-05-03 清华大学 存储区域网络中分布式虚拟化存储的方法
CN1282067C (zh) * 2004-08-09 2006-10-25 威盛电子股份有限公司 进行硬盘阵列同位运算的装置与相关方法
TWI344602B (en) * 2005-01-13 2011-07-01 Infortrend Technology Inc Redundant storage virtualization computer system
US7543096B2 (en) * 2005-01-20 2009-06-02 Dot Hill Systems Corporation Safe message transfers on PCI-Express link from RAID controller to receiver-programmable window of partner RAID controller CPU memory
GB0514529D0 (en) 2005-07-15 2005-08-24 Ibm Virtualisation engine and method, system, and computer program product for managing the storage of data
US8595313B2 (en) * 2005-11-29 2013-11-26 Netapp. Inc. Systems and method for simple scale-out storage clusters
CN100423491C (zh) 2006-03-08 2008-10-01 杭州华三通信技术有限公司 虚拟化网络存储系统及其网络存储设备
CN100581172C (zh) * 2006-04-19 2010-01-13 杭州华三通信技术有限公司 一种对目的磁盘进行访问的方法和扩展磁盘容量的系统
US20090089464A1 (en) * 2007-09-27 2009-04-02 Sun Microsystems, Inc. Modular i/o virtualization for blade servers
US8074021B1 (en) * 2008-03-27 2011-12-06 Netapp, Inc. Network storage system including non-volatile solid-state memory controlled by external data layout engine
TW201015336A (en) * 2008-10-03 2010-04-16 Accusys Technology Ltd Shared-storage bus switch

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070098001A1 (en) * 2005-10-04 2007-05-03 Mammen Thomas PCI express to PCI express based low latency interconnect scheme for clustering systems
CN1821946A (zh) * 2006-02-16 2006-08-23 杭州华为三康技术有限公司 一种存储系统以及存储数据的方法和读取数据的方法
CN101149664A (zh) * 2007-10-26 2008-03-26 华为技术有限公司 固态硬盘及处理其管理数据的方法

Also Published As

Publication number Publication date
EP2378430A1 (en) 2011-10-19
CN101763221A (zh) 2010-06-30
EP2378430A4 (en) 2011-10-26
CN101763221B (zh) 2013-01-30
US20110264833A1 (en) 2011-10-27
US8296476B2 (en) 2012-10-23

Similar Documents

Publication Publication Date Title
WO2010072113A1 (zh) 一种存储方法、存储系统及控制器
US10095639B2 (en) Multi-processor startup system
WO2018076793A1 (zh) 一种NVMe数据读写方法及NVMe设备
US20150127691A1 (en) Efficient implementations for mapreduce systems
TWI557570B (zh) 記憶體映射方法和記憶體映射系統
US9253275B2 (en) Cognitive dynamic allocation in caching appliances
CN114546913B (zh) 一种基于pcie接口的多主机之间数据高速交互的方法和装置
WO2014056178A1 (zh) 内存系统、内存模块、内存模块的访问方法以及计算机系统
US11449456B2 (en) System and method for scheduling sharable PCIe endpoint devices
JP6445710B2 (ja) マルチモード・システム・オン・チップ
JP7317727B2 (ja) 複数のチップ間の通信をサポートする方法、装置、電子機器およびコンピューター記憶媒体
EP3716084A1 (en) Apparatus and method for sharing a flash device among multiple masters of a computing platform
JP2020035453A (ja) I/oステアリングエンジンを備えるシステムオンチップ
US20190007483A1 (en) Server architecture having dedicated compute resources for processing infrastructure-related workloads
EP4123649A1 (en) Memory module, system including the same, and operation method of memory module
KR20120037785A (ko) 부하 균형을 유지하는 시스템 온 칩 및 그것의 부하 균형 유지 방법
US9047264B2 (en) Low pin count controller
US9733988B1 (en) Systems and methods to achieve load balancing among a plurality of compute elements accessing a shared memory pool
WO2012103768A1 (zh) 数据处理方法及装置、pci-e总线系统、服务器
US9921753B2 (en) Data replication across host systems via storage controller
TWI797022B (zh) 儲存控制器、計算儲存裝置以及計算儲存裝置的操作方法
WO2019223445A1 (zh) 硬盘读写控制方法、装置、电子设备及存储介质
JP2018524697A (ja) ネットワークラインカード(lc)のホストオペレーティングシステム(os)への統合
TWI567638B (zh) 多核心處理器、多核心處理系統、及初始化處理核心之方法
CN114546902A (zh) 基于多协议访问存储器的系统、设备和方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 09834066

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

WWE Wipo information: entry into national phase

Ref document number: 2009834066

Country of ref document: EP