WO2010022814A1 - Stiffening layers for the relaxation of strained layers - Google Patents
Stiffening layers for the relaxation of strained layers Download PDFInfo
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- WO2010022814A1 WO2010022814A1 PCT/EP2009/004790 EP2009004790W WO2010022814A1 WO 2010022814 A1 WO2010022814 A1 WO 2010022814A1 EP 2009004790 W EP2009004790 W EP 2009004790W WO 2010022814 A1 WO2010022814 A1 WO 2010022814A1
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- Prior art keywords
- layer
- strained material
- stiffening
- strained
- material layer
- Prior art date
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- 239000000463 material Substances 0.000 claims abstract description 171
- 238000010438 heat treatment Methods 0.000 claims abstract description 44
- 238000000034 method Methods 0.000 claims abstract description 35
- 230000002040 relaxant effect Effects 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims description 47
- 238000000059 patterning Methods 0.000 claims description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 11
- 239000004065 semiconductor Substances 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 9
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- 229910052796 boron Inorganic materials 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 229910052681 coesite Inorganic materials 0.000 claims description 6
- 229910052906 cristobalite Inorganic materials 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 229910052682 stishovite Inorganic materials 0.000 claims description 6
- 229910052905 tridymite Inorganic materials 0.000 claims description 6
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- 229910004541 SiN Inorganic materials 0.000 claims 1
- 239000010408 film Substances 0.000 description 10
- 230000008569 process Effects 0.000 description 7
- 230000005693 optoelectronics Effects 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000008602 contraction Effects 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 230000009477 glass transition Effects 0.000 description 3
- 238000001534 heteroepitaxy Methods 0.000 description 3
- 229910052738 indium Inorganic materials 0.000 description 3
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 3
- 229910052594 sapphire Inorganic materials 0.000 description 3
- 239000010980 sapphire Substances 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910002056 binary alloy Inorganic materials 0.000 description 2
- 239000005388 borosilicate glass Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229910002059 quaternary alloy Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910002058 ternary alloy Inorganic materials 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000001627 detrimental effect Effects 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 125000004437 phosphorous atom Chemical group 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 238000007669 thermal treatment Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000011282 treatment Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02488—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/0242—Crystalline insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/0254—Nitrides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
Definitions
- the present invention relates to the field of strained layers and compliant substrates for application in the manufacture of semiconductor devices useful in electronic, optoelectronic, photovoltaic field and, in particular, to the relaxation of strained films by the use of compliant substrates.
- the above-mentioned problem is solved by the method for relaxing a strained material layer according to claim 1.
- the method comprises the steps:
- a strained material layer and a low-viscosity layer comprising a compliant material and formed on a first face of the strained material layer
- the term "low-viscosity" is used to indicate deformation ability of the thus specified layer during the heat treatment (see also discussion below).
- the heat treatment thermal treatment, annealing
- the low-viscosity layer can, e.g., be a buried layer comprising borophosphosilicate glass that reflows under heat treatment.
- the buried layer may, for example, be an oxide layer.
- the multilayer stack may also include some support substrate on which the low-viscosity layer was formed (see detailed description below).
- a stiffening layer is provided partially atop of the strained material layer.
- the compressively strained material layer that are exposed can freely expand laterally thereby relaxing strain without significant buckling.
- the percentage of relaxation of the strained material layer during heat treatment can readily be controlled.
- the material exposed may freely contract while keeping its flatness, without forming crack or surface roughness.
- the step of the formation of the stiffening layer may comprise depositing the stiffening layer as a continuous layer on the entire surface of the strained material layer and subsequently patterning the deposited stiffening layer such that the stiffening layer is partially removed from the strained material layer.
- the patterning may be performed such that the stiffening layer partially covers the strained material layer and exposing the strained material layer at the edges. Patterning can be achieved by dry etching and photolithography and results in islands (stiffening islands) of the stiffening layer atop of the strained material layer. This kind of patterning can, thus, be readily achieved in a reliable and relatively time-saving way.
- the dimensions of the stiffening islands can be exactly controlled by the usage of photolithography. It is assumed that the portions of the strained material layer underneath the stiffening islands are not or almost not relaxed during the heat treatment.
- the subsequently performed steps of patterning the stiffening layer and subjecting the multilayer stack to the heat treatment are repeated in this order at least once.
- the original continuous stiffening layer is patterned to obtain the above-mentioned stiffening islands at a predetermined size and, then, a first heat treatment is performed in order to relax the portions of the strained material layer that are not covered by the stiffening islands.
- the sizes of the stiffening islands are reduced and a second heat treatment is carried out thereby relaxing portions of the strained material layer that were covered by the stiffening islands during the first heat treatment process.
- the repeated patterning and heat treatment can be performed until the desired degree (percentage) of relaxation of the strained material layer is achieved (which can very accurately be controlled by this sequence of processing) or, in particular, until no residuals of the stiffening islands are left and/or complete relaxation of the strained material layer is achieved. Different from the art complete relaxation can be achieved by the repeated heat treatments with different sizes of stiffening islands without causing significant buckling or other defects of the strained material layer.
- the strained material layer may also be patterned, in particular, by etching one or more trenches thereby forming strained material islands in order to facilitate the relaxation.
- the low-viscosity layer may be patterned in accordance with the strained material layer.
- one or more trenches might be etched through the strained material layer and the low-viscosity layer down to a support substrate on that the low-viscosity layer was deposited or to which it was bonded beforehand. The trenches may also be performed within the low-viscosity without reaching the support substrate.
- the stiffening layer can be patterned in such a way that islands of the stiffening layer are formed centered on islands of the strained material layer for an accurate control of the partial relaxation of the strained material islands.
- the islands made from the stiffening and the strained material layers may be shaped in rectangular, circular or any other form considered appropriate for the further the processing.
- strained material may refer to a continuous layer of a patterned layer exhibiting islands, where it is appropriate.
- the present invention proves particularly advantageous when the strained material layer comprises or consists of InGaN.
- the content of Indium in In- GaN material may be up to 35%, preferably the content of indium may be less than 10% and more preferably the content may be between 4 and 7%.
- the low-viscosity layer may comprise or consist of borophosphosilicate glass (BPSG) or an Si ⁇ 2 - compound comprising boron or phosphorous.
- BPSG borophosphosilicate glass
- Si ⁇ 2 - compound comprising boron or phosphorous.
- BSG borosilicate glass
- PSG phosphosilicate glass
- the reflow characteristics can be con- trolled by the content of boron and phosphorous atoms. 4 - 5 % of weight boron 2 % of weight phosphorous represent appropriate choices.
- the material of the stiffening layer shall be chosen according to the mechanical ability to suppress strain relaxation of the portions of the strained material layer that are covered by the stiffening (islands). Moreover, a more rigid material allows for a thinner stiffening layer, whereas a less rigid material raises the need for a thicker layer in order to obtain the desired partial stiffening of the strained material layer during the heat treatment.
- a stiffening layer may have a thickness from 50 nm and up to 5 times the thickness of the strained layer.
- the stiffening layer comprises or consists of Hl-N materials, SiN (Si 3 N 4 or SiN:H,) SiON or SiO 2 which proves a reliable stiffening means particularly in the case of a strained InGaN layer formed over a buried layer comprising bo- rophosphosilicate glass or an SiO 2 - compound comprising boron or phosphorous.
- the stiffening layer in particular, a stiffening layer of Si 3 N 4 , can be deposited with a thickness of between 100 nm to 300 nm in order to reliably suppress buckling of the strained material layer of about 100 nm thickness during the relaxing heat treatment.
- the stiffening layer may also be deposited with a thickness of up to 5 times the thickness of the strained material layer.
- the steps of patterning the stiffening layer and performing heat treatment of the multilayer stack comprising both the strained material layer and the stiffening layer might be repeated once or several times.
- Each subsequent heat treatment is performed for a larger exposed (not covered by the stiffening islands) area of the strained material layer.
- the measurement of exposed area to relax may be adjusted depending for example on the capability of the low viscosity layer to reflow, the temperature used and also the Young's modulus of the strained material.
- each step of patterning of the stiffening layer about 100 ⁇ m to 400 ⁇ m of the stiffening material in removed in one lateral dimension.
- the strained material layer in particular, a strained InGaN layer
- a strained InGaN layer is exposed between islands of the patterned stiffening layer, in particular, consisting Of Si 3 N 4 , in one lateral dimension.
- the entire surface of the strained material layer can, thus, by and by be exposed and can relax during the sequence of heat treatment processing.
- the final heat treatment may be performed with no stiffening layer remaining on the strained material layer.
- the thickness of the low-viscosity layer can be chosen less than the expansion length or contraction length of the strained material layer during the heat treatment without causing buckling or cracking of the film.
- the expansion / contraction length is the length of lateral expansion / contraction during the elastic relaxation of the strained material and plastic deformation of the low-viscosity layer caused by the heat treatment.
- the above- described methods further comprise:
- the low-viscosity layer When the low-viscosity layer is deposited on or bonded to some support substrate this support substrate is also detached together with the low-viscosity layer.
- the surface opposing the surface of the relaxed strained material layer on which the stiffening layer was deposited becomes available for further processing, in particular, for epitaxy of material layers.
- the strained material when the strained material is polar, as for the c-plane Ill/N material, the polarity of the face of the relaxed strained material opposing the face of growth on the seed substance that is suitable for any subsequent epitaxial growth of layers can be exposed.
- active layer(s) may be formed on the surface of the relaxed strained material for application in opto-electronic or photovoltaic field.
- the strained material layer of the above examples can be provided by heteroepitaxial growth.
- the strained material layer in particular, a strained InGaN layer
- the strained material layer can be grown directly on a seed substrate or on a seed layer, in particular, a GaN layer, that is deposited on or attached to a seed support substrate in particular, a sapphire support substrate before the step of depositing the low-viscosity layer comprising the compliant material layer, in particular, borophosphosilicate glass, on the strained material layer; and the strained material layer may be detached from the seed substrate (layer) and bonded by the low-viscosity layer to a support substrate before depositing the stiffening layer, in particular, comprising Si 3 N 4 , on the strained material layer.
- the GaN seed layer detached with the strained material from the seed support substrate may also be the stiffening layer.
- the herein disclosed method for relaxing a strained material layer is useful for the manufacture of semiconductor devices, in particular, opto-electronic devices or photovoltaic devices.
- a method for the manufacture of a semiconductor device comprising relaxing the strained material according to one of the preceding claims, and further comprising removing any residual parts of the stiffening layer so that the entire surface of the strained material is exposed and subjected to the heat treatment and epitaxially growing material layers on the formed at least partially relaxed strained material, in particular, growing active layers on the at least partially relaxed strained material islands.
- a semiconductor structure comprising a support substrate, a low-viscosity layer on the substrate, a continuous strained material layer or strained material islands on the low-viscosity layer, in particular, of InGaN material, and a stiffening layer partially covering the continuous strained material layer or the strained material islands, in particular, allowing 100 to 400 micrometers of exposed width of the strained material layer or the strained material islands.
- Figure 1 illustrates an example of the inventive method for relaxing a strained material layer comprising the formation of a patterned stiffening layer atop of the strained material layer.
- Figure 2 illustrates another example of the inventive method for relaxing strained material islands wherein stiffening islands are formed atop of the strained material islands.
- Figure 3 illustrates another example of the inventive method for relaxing strained material islands wherein stiffening islands are formed atop of strained material islands formed over a patterned compliant substance.
- Figure 1 shows an example of a multilayer stack formed according to the present invention.
- the multilayer stack comprises a support substrate 1 , a low-viscosity layer 2, a strained material layer 3 and a patterned stiffening layer 4.
- the strained material layer 3 was heteroepitaxially grown on some seed substrate and transferred to the support substrate 1 by any wafer transfer process known in the art, e.g., by grind/etch back, by laser lift off, electromagnetic irradiation absorption or ion implantation within the SMART Cut® process.
- the low-viscosity layer 2 is a buried layer, e.g. a buried oxide layer, that may be composed of different individual layers and comprises at least a compliant layer (relaxing layer).
- the compliant layer includes without limitation borophosphosilicate glass (BPSG) or an SiO 2 - compound comprising boron or phosphorus.
- BPSG borophosphosilicate glass
- the reflow rate during heat treatment can readily be adjusted by the boron and phosphorus content.
- the patterned stiffening layer 4 is obtained by deposition of a stiffening layer and etching by means of photolithography. Thereby, the strained material layer 3 is exposed at the lateral edges.
- Heat (thermal) treatment at glass transition temperature of the relaxing layer i.e. of about 800 0 C to 850 0 C for BPSG results in a partial elastic relaxation of the strained material layer 3 consisting of InGaN, for instance.
- an intact completely relaxed strained material layer is achieved that can be used for subsequent (ho- mo)epitaxy of a crystalline layer, e.g., an InGaN layer, that can to be employed in the manufacture of a particular semiconductor device useful in electronic or optoelectronic applications as well as the manufacture of solar cells.
- a crystalline layer e.g., an InGaN layer
- the completely relaxed strained material layer 3 may be transferred from the support substrate 1 to another substrate, e.g., by means of another buried layer deposited on the other substrate.
- the face Ga of relaxed strained c-plane InGaN material is preferred for epitaxial growth of crystalline layer.
- the multilayer stack shown in Figure 2 was formed in some detail as follows.
- a strained material layer was heteroepitaxially grown on a seed layer deposited on or bonded to a first support substrate.
- the strained material layer is an InGaN layer
- the seed layer is a GaN layer
- the first support substrate is a sapphire substrate, for instance.
- InGaN represents only one example for the material of the strained material layer.
- the strained material layer may be a semi-conductor material such as Ill/V material and may, for instance, comprise or consist of a Ill/N material chosen from a binary, ternary or quaternary alloy.
- the thickness of the strained InGaN layer is about 100 nm and the layer comprises about 4 % indium.
- the lattice mismatch of the heteroepitaxially grown strained InGaN layer 3 is about 0.4 %.
- a buried layer comprising a borophosphosilicate glass layer as a compliant (relaxation) material layer is deposited with a thickness of about 500 nm on the strained InGaN layer 3.
- an SiO 2 layer of a thickness of about 50 nm may be deposited on the strained InGaN layer in order to enhance the adherence between the gallium face of the strained c- plane InGaN layer and the buried layer.
- ionic species are implanted through the buried layer to form a weakened layer at about 400 nm in the InGaN/GaN materials.
- the weakened layer is provided in order to facilitate detachment of the seed layer and seed substrate.
- a second buried layer is deposited on the support substrate 1 shown in Figure 2. The thickness of the second buried layer is about 4 micrometers.
- the support substrate 1 and the strained InGaN layer are bonded by the first and the second buried layers that together form the low- viscosity layer 2 of Figure 2. After planarization and polishing before bonding the first and second buried layer, the thickness of the low-viscosity layer 2 is about 7 micrometers. After bonding the seed substrate is detached at the weakened layer and residual GaN material is removed by dry etching.
- the strained InGaN layer is patterned by lithography processing in order to form rectangular strained InGaN islands 3 of about 1 mm x 1 mm as shown in Figure 2.
- lithography processing in order to form rectangular strained InGaN islands 3 of about 1 mm x 1 mm as shown in Figure 2.
- Si 3 N 4 layer that functions as a stiffening layer during later heat treatment can, for instance, be achieved by plasma enhanced chemical vapor deposition (PECVD).
- PECVD plasma enhanced chemical vapor deposition
- the stiffening layer is patterned by dry etching with photolithography to form rectangular islands 4 sized from about 300 mi- crometers x 300 micrometers to about 400 micrometers x 400 micrometers and centered on the strained material islands 3.
- the low-viscosity layer 2 may have a thickness of about 4 micrometer, i.e. less than the expansion length of the strained InGaN islands 3, without affecting the relaxation quality.
- Figure 3 shows an example similar to the one described with reference to Figure 2 with the exception that both the low-viscosity layer and the strained material layer are patterned to form islands of the low-viscosity material 2 and strained material islands 3 separated by one or more trenches. Again, stiffening islands 4 are centered on the strained material islands 3. As described above heat treatment and further size reduction of the stiffening islands 4 may repeatedly be performed to achieve complete relaxation of the strained material islands 3 without buckling.
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Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/055,123 US8912081B2 (en) | 2008-08-25 | 2009-07-02 | Stiffening layers for the relaxation of strained layers |
JP2011524209A JP5505845B2 (en) | 2008-08-25 | 2009-07-02 | Hardened layer for strain layer relaxation |
KR1020117006815A KR101216367B1 (en) | 2008-08-25 | 2009-07-02 | Stiffening layers for the relaxation of strained layers |
CN200980132031.XA CN102124557B (en) | 2008-08-25 | 2009-07-02 | The lax strengthening course of strained layer |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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EP08290797.3A EP2159836B1 (en) | 2008-08-25 | 2008-08-25 | Stiffening layers for the relaxation of strained layers |
EP08290797.3 | 2008-08-25 |
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WO2010022814A1 true WO2010022814A1 (en) | 2010-03-04 |
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PCT/EP2009/004790 WO2010022814A1 (en) | 2008-08-25 | 2009-07-02 | Stiffening layers for the relaxation of strained layers |
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US (1) | US8912081B2 (en) |
EP (1) | EP2159836B1 (en) |
JP (1) | JP5505845B2 (en) |
KR (1) | KR101216367B1 (en) |
CN (1) | CN102124557B (en) |
WO (1) | WO2010022814A1 (en) |
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WO2013078191A1 (en) | 2011-11-23 | 2013-05-30 | Medimmune, Llc | Binding molecules specific for her3 and uses thereof |
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TWI457984B (en) | 2008-08-06 | 2014-10-21 | Soitec Silicon On Insulator | Relaxation of strained layers |
FR3064820B1 (en) | 2017-03-31 | 2019-11-29 | Soitec | METHOD FOR ADJUSTING THE STRAIN CONDITION OF A PIEZOELECTRIC FILM |
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US20070298549A1 (en) * | 2006-06-23 | 2007-12-27 | Interuniversitair Microelektronica Centrum Vzw (Imec) | Method of fabricating a strained multi-gate transistor and devices obtained thereof |
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JP2820187B2 (en) * | 1992-04-16 | 1998-11-05 | 三星電子 株式会社 | Method for manufacturing semiconductor device |
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