TW200512848A - Transparent packaging in wafer level - Google Patents
Transparent packaging in wafer levelInfo
- Publication number
- TW200512848A TW200512848A TW092126690A TW92126690A TW200512848A TW 200512848 A TW200512848 A TW 200512848A TW 092126690 A TW092126690 A TW 092126690A TW 92126690 A TW92126690 A TW 92126690A TW 200512848 A TW200512848 A TW 200512848A
- Authority
- TW
- Taiwan
- Prior art keywords
- wafer
- wafer level
- backside
- extending traces
- transparent packaging
- Prior art date
Links
- 238000004806 packaging method and process Methods 0.000 title abstract 2
- 150000001875 compounds Chemical class 0.000 abstract 3
- 229920000642 polymer Polymers 0.000 abstract 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01023—Vanadium [V]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12044—OLED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3512—Cracking
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Laminated Bodies (AREA)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW092126690A TWI226090B (en) | 2003-09-26 | 2003-09-26 | Transparent packaging in wafer level |
US10/948,214 US20050095750A1 (en) | 2003-09-26 | 2004-09-24 | Wafer level transparent packaging |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW092126690A TWI226090B (en) | 2003-09-26 | 2003-09-26 | Transparent packaging in wafer level |
Publications (2)
Publication Number | Publication Date |
---|---|
TWI226090B TWI226090B (en) | 2005-01-01 |
TW200512848A true TW200512848A (en) | 2005-04-01 |
Family
ID=34546318
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW092126690A TWI226090B (en) | 2003-09-26 | 2003-09-26 | Transparent packaging in wafer level |
Country Status (2)
Country | Link |
---|---|
US (1) | US20050095750A1 (zh) |
TW (1) | TWI226090B (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104241149B (zh) * | 2013-06-18 | 2016-12-28 | 常州银河世纪微电子有限公司 | 一种半导体芯片的焊接方法 |
Families Citing this family (32)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI232560B (en) * | 2002-04-23 | 2005-05-11 | Sanyo Electric Co | Semiconductor device and its manufacture |
US7579681B2 (en) * | 2002-06-11 | 2009-08-25 | Micron Technology, Inc. | Super high density module with integrated wafer level packages |
TWI229435B (en) * | 2002-06-18 | 2005-03-11 | Sanyo Electric Co | Manufacture of semiconductor device |
TWI227550B (en) * | 2002-10-30 | 2005-02-01 | Sanyo Electric Co | Semiconductor device manufacturing method |
JP4401181B2 (ja) * | 2003-08-06 | 2010-01-20 | 三洋電機株式会社 | 半導体装置及びその製造方法 |
JP4703127B2 (ja) * | 2004-03-31 | 2011-06-15 | ルネサスエレクトロニクス株式会社 | 半導体ウェーハ、半導体チップおよびその製造方法 |
KR100556351B1 (ko) * | 2004-07-27 | 2006-03-03 | 동부아남반도체 주식회사 | 반도체 소자의 금속 패드 및 금속 패드 본딩 방법 |
TWI324800B (en) * | 2005-12-28 | 2010-05-11 | Sanyo Electric Co | Method for manufacturing semiconductor device |
TWI303870B (en) * | 2005-12-30 | 2008-12-01 | Advanced Semiconductor Eng | Structure and mtehod for packaging a chip |
KR100691398B1 (ko) * | 2006-03-14 | 2007-03-12 | 삼성전자주식회사 | 미소소자 패키지 및 그 제조방법 |
KR100817059B1 (ko) | 2006-09-11 | 2008-03-27 | 삼성전자주식회사 | 박형 반도체 패키지 제조방법 |
KR100769722B1 (ko) * | 2006-10-10 | 2007-10-24 | 삼성전기주식회사 | 이미지센서의 웨이퍼 레벨 칩 스케일 패키지 및 그제조방법 |
JP5028988B2 (ja) * | 2006-12-13 | 2012-09-19 | ヤマハ株式会社 | 半導体装置の製造方法 |
US20090026562A1 (en) * | 2007-07-26 | 2009-01-29 | Visera Technologies Company Limited | Package structure for optoelectronic device |
US7932179B2 (en) * | 2007-07-27 | 2011-04-26 | Micron Technology, Inc. | Method for fabricating semiconductor device having backside redistribution layers |
TWI375321B (en) * | 2007-08-24 | 2012-10-21 | Xintec Inc | Electronic device wafer level scale packages and fabrication methods thereof |
US7897502B2 (en) * | 2008-09-10 | 2011-03-01 | Stats Chippac, Ltd. | Method of forming vertically offset bond on trace interconnects on recessed and raised bond fingers |
US8236613B2 (en) * | 2010-05-24 | 2012-08-07 | Alpha & Omega Semiconductor Inc. | Wafer level chip scale package method using clip array |
DE102011112659B4 (de) * | 2011-09-06 | 2022-01-27 | Vishay Semiconductor Gmbh | Oberflächenmontierbares elektronisches Bauelement |
CN103065985B (zh) * | 2011-10-21 | 2015-04-22 | 中国科学院上海微系统与信息技术研究所 | 双面布线封装的圆片级大厚度光敏bcb背面制作方法 |
KR101419600B1 (ko) * | 2012-11-20 | 2014-07-17 | 앰코 테크놀로지 코리아 주식회사 | 지문인식센서 패키지 및 그 제조 방법 |
US10141202B2 (en) * | 2013-05-20 | 2018-11-27 | Qualcomm Incorporated | Semiconductor device comprising mold for top side and sidewall protection |
JP6189208B2 (ja) * | 2013-12-26 | 2017-08-30 | 株式会社ディスコ | ウエーハの加工方法 |
JP6325279B2 (ja) * | 2014-02-21 | 2018-05-16 | 株式会社ディスコ | ウエーハの加工方法 |
TWI529891B (zh) * | 2014-05-01 | 2016-04-11 | 精材科技股份有限公司 | 半導體結構及其製作方法 |
CN104795372A (zh) * | 2015-03-27 | 2015-07-22 | 江阴长电先进封装有限公司 | 一种指纹识别传感器芯片的封装结构 |
CN105552043A (zh) * | 2015-12-28 | 2016-05-04 | 江阴长电先进封装有限公司 | 一种指纹识别传感器的封装结构 |
DE102017122650B4 (de) * | 2017-09-28 | 2023-02-09 | Infineon Technologies Ag | Halbleiterchip einschliesslich einer selbstausgerichteten rückseitigen leitfähigen schicht und verfahren zum herstellen desselben |
CN109692828B (zh) * | 2019-02-18 | 2024-01-23 | 成都泰美克晶体技术有限公司 | 一种适用于1210封装尺寸的晶片挑选治具 |
US11201096B2 (en) | 2019-07-09 | 2021-12-14 | Texas Instruments Incorporated | Packaged device with die wrapped by a substrate |
FR3104317A1 (fr) | 2019-12-04 | 2021-06-11 | Stmicroelectronics (Tours) Sas | Procédé de fabrication de puces électroniques |
FR3126540A1 (fr) * | 2021-08-31 | 2023-03-03 | Stmicroelectronics (Tours) Sas | Procédé de fabrication de puces électroniques |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
IL108359A (en) * | 1994-01-17 | 2001-04-30 | Shellcase Ltd | Method and device for creating integrated circular devices |
US6693358B2 (en) * | 2000-10-23 | 2004-02-17 | Matsushita Electric Industrial Co., Ltd. | Semiconductor chip, wiring board and manufacturing process thereof as well as semiconductor device |
TWI232560B (en) * | 2002-04-23 | 2005-05-11 | Sanyo Electric Co | Semiconductor device and its manufacture |
TWI229435B (en) * | 2002-06-18 | 2005-03-11 | Sanyo Electric Co | Manufacture of semiconductor device |
-
2003
- 2003-09-26 TW TW092126690A patent/TWI226090B/zh not_active IP Right Cessation
-
2004
- 2004-09-24 US US10/948,214 patent/US20050095750A1/en not_active Abandoned
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104241149B (zh) * | 2013-06-18 | 2016-12-28 | 常州银河世纪微电子有限公司 | 一种半导体芯片的焊接方法 |
Also Published As
Publication number | Publication date |
---|---|
TWI226090B (en) | 2005-01-01 |
US20050095750A1 (en) | 2005-05-05 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
MK4A | Expiration of patent term of an invention patent |